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Intel 87C196CB, 8XC196NT user manual Memory Partitions

Models: 8XC196NT 87C196CB

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MEMORY PARTITIONS

Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs (Continued)

			32-byte Windows		64-byte Windows		128-byte Windows
	Register Mnemonic	Memory	(00E0–00FFH)		(00C0–00FFH)		(0080–00FFH)
		Memory
		Location	WSR	Direct	WSR	Direct	WSR	Direct
		Location

				Address		Address		Address
				Address		Address		Address

	CAN_MSG7CON0	1E70H	73H	00F0H	39H	00F0H	1CH	00F0H

	CAN_MSG8CON0	1E80H	74H	00E0H	3AH	00C0H	1DH	0080H

	CAN_MSG9CON0	1E90H	74H	00F0H	3AH	00D0H	1DH	0090H

	CAN_MSG10CON0	1EA0H	75H	00E0H	3AH	00E0H	1DH	00A0H

	CAN_MSG11CON0	1EB0H	75H	00F0H	3AH	00F0H	1DH	00B0H

	CAN_MSG12CON0	1EC0H	76H	00E0H	3BH	00C0H	1DH	00C0H

	CAN_MSG13CON0	1ED0H	76H	00F0H	3BH	00D0H	1DH	00D0H

	CAN_MSG14CON0	1EE0H	77H	00E0H	3BH	00E0H	1DH	00E0H

	CAN_MSG15CON0	1EF0H	77H	00F0H	3BH	00F0H	1DH	00F0H

	CAN_MSG1CON1	1E11H	70H	00F1H	38H	00D1H	1CH	0091H

	CAN_MSG2CON1	1E21H	71H	00E1H	38H	00E1H	1CH	00A1H

	CAN_MSG3CON1	1E31H	71H	00F1H	38H	00F1H	1CH	00B1H

	CAN_MSG4CON1	1E41H	72H	00E1H	39H	00C1H	1CH	00C1H

	CAN_MSG5CON1	1E51H	72H	00F1H	39H	00D1H	1CH	00D1H

	CAN_MSG6CON1	1E61H	73H	00E1H	39H	00E1H	1CH	00E1H

	CAN_MSG7CON1	1E71H	73H	00F1H	39H	00F1H	1CH	00F1H

	CAN_MSG8CON1	1E81H	74H	00E1H	3AH	00C1H	1DH	0081H

	CAN_MSG9CON1	1E91H	74H	00F1H	3AH	00D1H	1DH	0091H

	CAN_MSG10CON1	1EA1H	75H	00E1H	3AH	00E1H	1DH	00A1H

	CAN_MSG11CON1	1EB1H	75H	00F1H	3AH	00F1H	1DH	00B1H

	CAN_MSG12CON1	1EC1H	76H	00E1H	3BH	00C1H	1DH	00C1H

	CAN_MSG13CON1	1ED1H	76H	00F1H	3BH	00D1H	1DH	00D1H

	CAN_MSG14CON1	1EE1H	77H	00E1H	3BH	00E1H	1DH	00E1H

	CAN_MSG15CON1	1EF1H	77H	00F1H	3BH	00F1H	1DH	00F1H

	CAN_MSG1DATA0	1E17H	70H	00F7H	38H	00D7H	1CH	0097H

	CAN_MSG2DATA0	1E27H	71H	00E7H	38H	00E7H	1CH	00A7H

	CAN_MSG3DATA0	1E37H	71H	00F7H	38H	00F7H	1CH	00B7H

	CAN_MSG4DATA0	1E47H	72H	00E7H	39H	00C7H	1CH	00C7H

	CAN_MSG5DATA0	1E57H	72H	00F7H	39H	00D7H	1CH	00D7H

	CAN_MSG6DATA0	1E67H	73H	00E7H	39H	00E7H	1CH	00E7H

	CAN_MSG7DATA0	1E77H	73H	00F7H	39H	00F7H	1CH	00F7H

	CAN_MSG8DATA0	1E87H	74H	00E7H	3AH	00C7H	1DH	0087H

†Must be addressed as a word.

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Intel 87C196CB, 8XC196NT user manual Memory Partitions

Contents

87C196CB Supplement to 8XC196NT User’s Manual 87C196CB Supplement to 8XC196NT User’s Manual AugustOrder Number Copyright Intel Corporation, 1998 CONTENTS CHAPTERGUIDE TO THIS MANUAL CHAPTERSIGNAL DESCRIPTIONS 87C196CB SUPPLEMENTCHAPTER SPECIAL OPERATING MODESFIGURES CONTENTSInternal Clock Phases Effect of Clock Mode on CLKOUT FrequencyFIGURES 8XC196CB SUPPLEMENTPage 87C196CB 100-pin QFP PackageTABLES CONTENTSPage Page Guide to This Manual Page 1.1 MANUAL CONTENTS CHAPTER GUIDE TO THIS MANUAL1.2 RELATED DOCUMENTS Appendix A - Signal DescriptionsChapter 9 - Interfacing with External Memory Architectural Overview Page 2.1 DEVICE FEATURES CHAPTER ARCHITECTURAL OVERVIEW2.2 BLOCK DIAGRAM 2.3 INTERNAL TIMINGPage 8 MHz 12 MHz16 MHz 20 MHzFigure 2-4. Effect of Clock Mode on CLKOUT Frequency ARCHITECTURAL OVERVIEWFrequency Input Frequency toPage Memory Partitions Page CHAPTER MEMORY PARTITIONS 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map AddressTimer 1, Timer 2, and EPA SFRs MEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRsPorts 0, 1, 2, and 6 SFRs SIO and SSIO SFRs87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs 1EDCH1ECCH MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued Message87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs 32-byte Window64-byte Window 128-byte WindowMEMORY PARTITIONS Table 3-6. Selecting a Window of the Upper Register FileRegister RAM Locations87C196CB SUPPLEMENT MEMORY PARTITIONS Table 3-7. Selecting a Window of Upper Register RAM0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows MEMORY PARTITIONS Table 3-8. Windows ContinuedUpper Register File Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs 87C196CB SUPPLEMENTMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 32-byte Windows64-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page CHAPTER STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES87C196CB SUPPLEMENT Figure 4-1. Interrupt Mask 1 INTMASK1 RegisterFigure 4-2. interrupt Pending 1 INTPEND1 Register Standard VectorI/O Ports Page CHAPTER I/O PORTS 5.1 PORT 0 AND EPORTFigure 5-3. Extended Port Mode EPMODE Register 87C196CB SUPPLEMENTFigure 5-2. Extended Port I/O Direction EPDIR Register EPDIRI/O PORTS Figure 5-4. Extended Port Input EPPIN RegisterFigure 5-5. Extended Port Data Output EPREG Register EPPINPage Analog-to-digital A/D Converter Page CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELSFigure 6-1. A/D Command ADCOMMAND Register ADCOMMAND87C196CB SUPPLEMENT FunctionANALOG-TO-DIGITAL A/D CONVERTER Figure 6-2. A/D Result ADRESULT Register - Read FormatADRESULT Read FunctionPage CAN Serial Communications Controller Page CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.1 CAN FUNCTIONAL OVERVIEWPage 7.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7-1. CAN Controller SignalsCAN SERIAL COMMUNICATIONS CONTROLLER Table 7-2. Control and Status Registers7.3 CAN CONTROLLER OPERATION 87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued7.3.1 Address Map 7.3.2 Message ObjectsContents 87C196CB SUPPLEMENT Table 7-4. Message Object Structure7.3.2.1 Receive and Transmit Priorities 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Table 7-7. Extended Message Frame7.3.4 Error Detection and Management Logic 7.3.5 Bit Timing SymbolDefinition CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-5. A Bit Time as Implemented in the CAN ControllerTable 7-9. CAN Controller Bit Time Segments t SYNCwhere Table 7-10 defines the bit timing relationships of the CAN controller87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations Table 7-10. Bit Timing Relationships7.4 CONFIGURING THE CAN CONTROLLER 7.4.1 Programming the CAN Control CANCON RegisterThis bit globally enables and disables interrupts error, status-change, and 87C196CB SUPPLEMENTFigure 7-6. CAN Control CANCON Register Continued 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register Unchanged7.4.3 Programming the Bit Timing 1 CANBTIME1 Register 87C196CB SUPPLEMENTFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register TSEG27.4.4 Programming a Message Acceptance Filter Bit TimeRequirement Comments87C196CB SUPPLEMENT Figure 7-9. CAN Standard Global Mask CANSGMSK RegisterCANSGMSK 87C196CBCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-10. CAN Extended Global Mask CANEGMSK RegisterCANEGMSK 87C196CB7.5 CONFIGURING MESSAGE OBJECTS 87C196CB SUPPLEMENTFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 7.5.2 Programming the Message Object Identifier 87C196CB SUPPLEMENTFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.3 Programming the Message Object Control Registers 7.5.4 Programming the Message Object DataAccess Type 87C196CB SUPPLEMENT Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 RegisterProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 RegisterCAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 RegistersFunction 7.6 ENABLING THE CAN INTERRUPTS 87C196CB SUPPLEMENT Figure 7-17. CAN Control CANCON Register ContinuedCANCON Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-20. CAN Status CANSTAT Register87C196CB SUPPLEMENT Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register7.8 FLOW DIAGRAMS Register MnemonicProcess message contents 87C196CB SUPPLEMENTFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow A2594-01CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-23. Receiving a Message for Message Object 15 - CPU FlowRestart Process 87C196CB SUPPLEMENT Figure 7-24. Receiving a Message - CAN Controller FlowReceived frame with same identifer as thisPower Up UpdateCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-25. Transmitting a Message - CPU Flow87C196CB SUPPLEMENT Figure 7-26. Transmitting a Message - CAN Controller FlowReceived remote frame with same identifer as7.9.1 Hardware Reset 7.9 DESIGN CONSIDERATIONS7.9.2 Software Initialization 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page CHAPTER SPECIAL OPERATING MODES 8.1 CLOCK CIRCUITRYFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page 9.1 ADDRESS PINS CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY9.2 BUS TIMING MODES 87C196CB SUPPLEMENT Figure 9-1. Modes 0 and 3 TimingsT RLDV = 1t T AVDV = 3tFigure 9-2. Chip Configuration 1 CCR1 Register no direct access †= always enabled INTERFACING WITH EXTERNAL MEMORYFigure 9-2. Chip Configuration 1 CCR1 Register Continued 87C196CB SUPPLEMENTCCR1 Continued FunctionProgramming the Nonvolatile Memory Page 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory MapTable 10-3. Auto Programming Memory Map 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMING PROGRAMMING THE NONVOLATILE MEMORYFigure 10-1. Auto Programming Circuit 74HC1410.4.1 Selecting Bank 0 FF2000-FF7FFFH 10.4.2 Selecting Bank 1 FF8000-FFFFFFHSerial Port Programming Mode Signal Descriptions Page APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALS87C196CB Supplement Figure A-1. 87C196CB 84-pin PLCC Packagexx87C196CB View of component asA.2 SIGNAL DESCRIPTIONS SIGNAL DESCRIPTIONSFigure A-2. 87C196CB 100-pin QFP Package xx87C196CBTable A-3. Signal Descriptions 87C196CB SupplementTable A-2. Description of Columns of Table A-3 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions Continuedread or write. AINC# is sampled after each location is programmed or dumped Table A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementA-10 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-11 Table A-3. Signal Descriptions Continued 87C196CB SupplementA-12 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-13 A.3 DEFAULT CONDITIONS Table A-3. Signal Descriptions ContinuedTable A-4. Definition of Status Symbols 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-5. 87C196CB Pin Status ContinuedA-15 Page Glossary Page GLOSSARY transfer function of an A/D converter two adjacent code transitions on the A/D converterchannel-to-channel matching error characteristicearity errors See off-isolationconversion result. Differential nonlinearity is a code widthThe characteristic of an ideal A/D converter. An ideal linearity errors. Quantizing error is the only errorare to be serviced by interrupt service routines that starting address of an interrupt service routineSee interrupt service routine See differential nonlinearity and nonlinearitylinearity errors terminal-based characteristic from the corre serviced by interrupt service routines that youOTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determinedirectly to the interrupt service routine when See PTS control blockprioritized interrupt transitions from different actual characteristics taken ideal A/D converterquantizing error repeatability errorSuccessive approximation register. A component of the A/D convertersample delay service routine scaled to remove zero-offset error and full-scalecharacteristic of the A/D converter interrupt controller for processing by an interruptprocess quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearityisolation, and VCC rejection errors characteristicPage Index Page INDEX 87C196CB SUPPLEMENT Index-2