Intel 87C196CB Prioritized interrupt, Program memory, Protected instruction, PTS control block

	GLOSSARY
prioritized interrupt	Any maskable interrupt or nonmaskable NMI. Two of
	the nonmaskable interrupts (unimplemented opcode
	and software trap) are not prioritized; they vector
	directly to the interrupt service routine when
	executed.
program memory	A partition of memory where instructions can be
	stored for fetching and execution.
protected instruction	An instruction that prevents an interrupt from being
	acknowledged until after the next instruction
	executes. The protected instructions are DI, EI,
	DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF.
PSW	Processor status word. The high byte of the PSW is
	the status byte, which contains one bit that globally
	enables or disables servicing of all maskable
	interrupts, one bit that enables or disables the PTS,
	and six Boolean flags that reflect the state of the
	current program. The low byte of the PSW is the
	INT_MASK register. A push or pop instruction saves
	or restores both bytes (PSW + INT_MASK).
PTS	Peripheral transaction server. The microcoded
	hardware interrupt processor.
PTSCB	See PTS control block.
PTS control block	A block of data required for each PTS interrupt. The
	microcode executes the proper PTS routine based on
	the contents of the PTS control block.
PTS cycle	The microcoded response to a single PTS interrupt
	request.
PTS interrupt	Any maskable interrupt that is assigned to the PTS for
	interrupt processing.
PTS mode	A microcoded response that enables the PTS to
	complete a specific task quickly. These tasks include
	transferring a single byte or word, transferring a block
	of bytes or words, managing multiple A/D conver-
	sions, and generating PWM outputs.
PTS routine	The entire microcoded response to multiple PTS
	interrupt requests. The PTS routine is controlled by
	the contents of the PTS control block.

Glossary-7