Intel 87C196CB Architectural Overview, 4. Effect of Clock Mode on CLKOUT Frequency, on XTAL1

ARCHITECTURAL OVERVIEW

PLLEN = 0

XTAL1 (5 MHz)

t = 80ns

f

TXHCH

CLKOUT

PLLEN = 1

XTAL1 (5 MHz)

t = 20ns

f

TXHCH

CLKOUT

A3170-01

Figure 2-4. Effect of Clock Mode on CLKOUT Frequency

Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times

FXTAL1	PLLEN	Multiplier	f	t	State Time
(Frequency			(Input Frequency to	(Clock
on XTAL1)			the Divide-by-two Circuit)	Period)
4 MHz	0	1	4 MHz	250 ns	500 ns
5 MHz	0	1	5 MHz	200 ns	400 ns
8 MHz	0	1	8 MHz	125 ns	250 ns
12 MHz	0	1	12 MHz	83.5 ns	167 ns
16 MHz	0	1	16 MHz	62.5 ns	125 ns
20 MHz	0	1	20 MHz	50 ns	100 ns
4 MHz	1	4	16 MHz	62.5 ns	125 ns
5 MHz	1	4	20 MHz	50 ns	100 ns

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