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Intel 87C196CB Chapter Standard And Pts Interrupts, Interrupt Sources, Vectors, And Priorities

Models: 8XC196NT 87C196CB

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CHAPTER 4

CHAPTER 4

STANDARD AND PTS INTERRUPTS

4.1INTERRUPT SOURCES, VECTORS, AND PRIORITIES

The interrupt structure of the 87C196CB is the same as that of the 8XC196NT. The only differ- ence is that INT13, which was reserved on the 8XC196NT, supports the CAN peripheral.

Table 4-1 lists the 87C196CB’s interrupts sources, default priorities (30 is highest and 0 is low- est), and vector addresses. Figures 4-1 and 4-2 illustrate the interrupt mask and pending registers.

Table 4-1. Interrupt Sources, Vectors, and Priorities

			Interrupt Controller			PTS Service
				Service		PTS Service
				Service

Interrupt Source	Mnemonic

Nonmaskable Interrupt	NMI		INT15	FF203EH	30	—	—		—
EXTINT Pin	EXTINT		INT14	FF203CH	14	PTS14	FF205CH		29
CAN	CAN		INT13	FF203AH	13	PTS13 †	FF205AH		28
SIO Receive	RI		INT12	FF2038H	12	PTS12	FF2058H		27
SIO Transmit	TI		INT11	FF2036H	11	PTS11	FF2056H		26
SSIO Channel 1 Transfer	SSIO1		INT10	FF2034H	10	PTS10	FF2054H		25
SSIO Channel 0 Transfer	SSIO0		INT09	FF2032H	09	PTS09	FF2052H		24
Slave Port Command Buff Full	CBF		INT08	FF2030H	08	PTS08	FF2050H		23
Unimplemented Opcode	—		—	FF2012H	—	—	—	—
Software TRAP Instruction	—		—	FF2010H	—	—	—	—
Slave Port Input Buff Full	IBF		INT07	FF200EH	07	PTS07	FF204EH		22
Slave Port Output Buff Empty	OBE		INT06	FF200CH	06	PTS06	FF204CH		21
A/D Conversion Complete	AD_DONE		INT05	FF200AH	05	PTS05	FF204AH		20
EPA Capture/Compare 0	EPA0		INT04	FF2008H	04	PTS04	FF2048H		19
EPA Capture/Compare 1	EPA1		INT03	FF2006H	03	PTS03	FF2046H		18
EPA Capture/Compare 2	EPA2		INT02	FF2004H	02	PTS02	FF2044H		17
EPA Capture/Compare 3	EPA3		INT01	FF2002H	01	PTS01	FF2042H		16
EPA Capture/Compare 4–9,	EPAx		INT00	FF2000H	00	PTS00†	FF2040H		15
EPA 0–9 Overrun,
EPA Compare 0–1,
Timer 1 Overflow,
Timer 2 Overflow

†PTS service is not recommended because the PTS cannot determine the source of shared interrupts.

4-1

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Intel 87C196CB, 8XC196NT user manual Chapter Standard And Pts Interrupts, Interrupt Sources, Vectors, And Priorities

Contents

87C196CB Supplement to 8XC196NT User’s Manual August 87C196CB Supplement to 8XC196NT User’s ManualOrder Number Copyright Intel Corporation, 1998 GUIDE TO THIS MANUAL CONTENTSCHAPTER CHAPTERCHAPTER SIGNAL DESCRIPTIONS87C196CB SUPPLEMENT SPECIAL OPERATING MODESInternal Clock Phases FIGURESCONTENTS Effect of Clock Mode on CLKOUT FrequencyPage FIGURES8XC196CB SUPPLEMENT 87C196CB 100-pin QFP PackageCONTENTS TABLESPage Page Guide to This Manual Page 1.1 MANUAL CONTENTS CHAPTER GUIDE TO THIS MANUALAppendix A - Signal Descriptions 1.2 RELATED DOCUMENTSChapter 9 - Interfacing with External Memory Architectural Overview Page 2.1 DEVICE FEATURES CHAPTER ARCHITECTURAL OVERVIEW2.2 BLOCK DIAGRAM 2.3 INTERNAL TIMINGPage 16 MHz 8 MHz12 MHz 20 MHzFrequency Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyARCHITECTURAL OVERVIEW Input Frequency toPage Memory Partitions Page CHAPTER MEMORY PARTITIONS 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map AddressPorts 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRsMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs SIO and SSIO SFRs1EDCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1ECCH MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued Message64-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs32-byte Window 128-byte WindowRegister RAM MEMORY PARTITIONSTable 3-6. Selecting a Window of the Upper Register File Locations87C196CB SUPPLEMENT Table 3-7. Selecting a Window of Upper Register RAM MEMORY PARTITIONS0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows Table 3-8. Windows Continued MEMORY PARTITIONSUpper Register File Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs 87C196CB SUPPLEMENTMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 64-byte Windows MEMORY PARTITIONS32-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page CHAPTER STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIESFigure 4-2. interrupt Pending 1 INTPEND1 Register 87C196CB SUPPLEMENTFigure 4-1. Interrupt Mask 1 INTMASK1 Register Standard VectorI/O Ports Page CHAPTER I/O PORTS 5.1 PORT 0 AND EPORTFigure 5-2. Extended Port I/O Direction EPDIR Register Figure 5-3. Extended Port Mode EPMODE Register87C196CB SUPPLEMENT EPDIRFigure 5-5. Extended Port Data Output EPREG Register I/O PORTSFigure 5-4. Extended Port Input EPPIN Register EPPINPage Analog-to-digital A/D Converter Page CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELS87C196CB SUPPLEMENT Figure 6-1. A/D Command ADCOMMAND RegisterADCOMMAND FunctionADRESULT Read ANALOG-TO-DIGITAL A/D CONVERTERFigure 6-2. A/D Result ADRESULT Register - Read Format FunctionPage CAN Serial Communications Controller Page CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.1 CAN FUNCTIONAL OVERVIEWPage CAN SERIAL COMMUNICATIONS CONTROLLER 7.2 CAN CONTROLLER SIGNALS AND REGISTERSTable 7-1. CAN Controller Signals Table 7-2. Control and Status Registers7.3 CAN CONTROLLER OPERATION 87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued7.3.1 Address Map 7.3.2 Message Objects7.3.2.1 Receive and Transmit Priorities Contents87C196CB SUPPLEMENT Table 7-4. Message Object Structure 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Table 7-7. Extended Message Frame7.3.4 Error Detection and Management Logic Symbol 7.3.5 Bit TimingDefinition Table 7-9. CAN Controller Bit Time Segments CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-5. A Bit Time as Implemented in the CAN Controller t SYNC87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations whereTable 7-10 defines the bit timing relationships of the CAN controller Table 7-10. Bit Timing Relationships7.4 CONFIGURING THE CAN CONTROLLER 7.4.1 Programming the CAN Control CANCON Register87C196CB SUPPLEMENT This bit globally enables and disables interrupts error, status-change, andFigure 7-6. CAN Control CANCON Register Continued 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register UnchangedFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register 7.4.3 Programming the Bit Timing 1 CANBTIME1 Register87C196CB SUPPLEMENT TSEG2Requirement 7.4.4 Programming a Message Acceptance FilterBit Time CommentsCANSGMSK 87C196CB SUPPLEMENTFigure 7-9. CAN Standard Global Mask CANSGMSK Register 87C196CBCANEGMSK CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-10. CAN Extended Global Mask CANEGMSK Register 87C196CB87C196CB SUPPLEMENT 7.5 CONFIGURING MESSAGE OBJECTSFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 87C196CB SUPPLEMENT 7.5.2 Programming the Message Object IdentifierFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.4 Programming the Message Object Data 7.5.3 Programming the Message Object Control RegistersAccess Type Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 RegisterCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 87C196CB SUPPLEMENTFunction 7.6 ENABLING THE CAN INTERRUPTS CANCON Continued 87C196CB SUPPLEMENTFigure 7-17. CAN Control CANCON Register Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-20. CAN Status CANSTAT Register87C196CB SUPPLEMENT Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register7.8 FLOW DIAGRAMS Register MnemonicFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow Process message contents87C196CB SUPPLEMENT A2594-01Figure 7-23. Receiving a Message for Message Object 15 - CPU Flow CAN SERIAL COMMUNICATIONS CONTROLLERRestart Process Received frame with 87C196CB SUPPLEMENTFigure 7-24. Receiving a Message - CAN Controller Flow same identifer as thisCAN SERIAL COMMUNICATIONS CONTROLLER Power UpUpdate Figure 7-25. Transmitting a Message - CPU FlowReceived remote frame 87C196CB SUPPLEMENTFigure 7-26. Transmitting a Message - CAN Controller Flow with same identifer as7.9.2 Software Initialization 7.9.1 Hardware Reset7.9 DESIGN CONSIDERATIONS 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page 8.1 CLOCK CIRCUITRY CHAPTER SPECIAL OPERATING MODESFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY 9.1 ADDRESS PINS9.2 BUS TIMING MODES T RLDV = 1t 87C196CB SUPPLEMENTFigure 9-1. Modes 0 and 3 Timings T AVDV = 3t= always enabled Figure 9-2. Chip Configuration 1 CCR1 Registerno direct access † INTERFACING WITH EXTERNAL MEMORYCCR1 Continued Figure 9-2. Chip Configuration 1 CCR1 Register Continued87C196CB SUPPLEMENT FunctionProgramming the Nonvolatile Memory Page CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMINGTable 10-3. Auto Programming Memory Map Figure 10-1. Auto Programming Circuit 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGPROGRAMMING THE NONVOLATILE MEMORY 74HC1410.4.2 Selecting Bank 1 FF8000-FFFFFFH 10.4.1 Selecting Bank 0 FF2000-FF7FFFHSerial Port Programming Mode Signal Descriptions Page APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALSxx87C196CB 87C196CB SupplementFigure A-1. 87C196CB 84-pin PLCC Package View of component asFigure A-2. 87C196CB 100-pin QFP Package A.2 SIGNAL DESCRIPTIONSSIGNAL DESCRIPTIONS xx87C196CB87C196CB Supplement Table A-3. Signal DescriptionsTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSread or write. AINC# is sampled after each location is programmed or dumped Table A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions Continued87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-10 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-11 87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-12 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-13 Table A-4. Definition of Status Symbols A.3 DEFAULT CONDITIONSTable A-3. Signal Descriptions Continued 87C196CB SupplementTable A-5. 87C196CB Pin Status Continued SIGNAL DESCRIPTIONSA-15 Page Glossary Page GLOSSARY channel-to-channel matching error transfer function of an A/D convertertwo adjacent code transitions on the A/D converter characteristicconversion result. Differential nonlinearity is a earity errorsSee off-isolation code widthare to be serviced by interrupt service routines that The characteristic of an ideal A/D converter. An ideallinearity errors. Quantizing error is the only error starting address of an interrupt service routineSee differential nonlinearity and nonlinearity See interrupt service routinelinearity errors OTPROM. Consult the Automotive Products or terminal-based characteristic from the correserviced by interrupt service routines that you Embedded Microcontrollers databook to determineSee PTS control block directly to the interrupt service routine whenprioritized interrupt quantizing error transitions from different actual characteristics takenideal A/D converter repeatability errorthe A/D converter Successive approximation register. A component ofsample delay characteristic of the A/D converter service routinescaled to remove zero-offset error and full-scale interrupt controller for processing by an interruptisolation, and VCC rejection errors process quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity characteristicPage Index Page INDEX 87C196CB SUPPLEMENT Index-2