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Intel 87C196CB, 8XC196NT user manual Memory Partitions, byte Windows, Register Mnemonic, Location

Models: 8XC196NT 87C196CB

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MEMORY PARTITIONS

Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs (Continued)

			32-byte Windows		64-byte Windows		128-byte Windows
	Register Mnemonic	Memory	(00E0–00FFH)		(00C0–00FFH)		(0080–00FFH)
		Memory
		Location	WSR	Direct	WSR	Direct	WSR	Direct
		Location

				Address		Address		Address
				Address		Address		Address

	CAN_MSG4ID3	1E45H	72H	00E5H	39H	00C5H	1CH	00C5H

	CAN_MSG5ID3	1E55H	72H	00F5H	39H	00D5H	1CH	00D5H

	CAN_MSG6ID3	1E65H	73H	00E5H	39H	00E5H	1CH	00E5H

	CAN_MSG7ID3	1E75H	73H	00F5H	39H	00F5H	1CH	00F5H

	CAN_MSG8ID3	1E85H	74H	00E5H	3AH	00C5H	1DH	0085H

	CAN_MSG9ID3	1E95H	74H	00F5H	3AH	00D5H	1DH	0095H

	CAN_MSG10ID3	1EA5H	75H	00E5H	3AH	00E5H	1DH	00A5H

	CAN_MSG11ID3	1EB5H	75H	00F5H	3AH	00F5H	1DH	00B5H

	CAN_MSG12ID3	1EC5H	76H	00E5H	3BH	00C5H	1DH	00C5H

	CAN_MSG13ID3	1ED5H	76H	00F5H	3BH	00D5H	1DH	00D5H

	CAN_MSG14ID3	1EE5H	77H	00E5H	3BH	00E5H	1DH	00E5H

	CAN_MSG15ID3	1EF5H	77H	00F5H	3BH	00F5H	1DH	00F5H

	CAN_MSK15	1E0CH	70H	00ECH	38H	00CCH	1CH	008CH

	CAN_SGMSK	1E06H	70H	00E6H	38H	00C6H	1CH	0086H

	CAN_STAT	1E01H	70H	00E1H	38H	00C1H	1CH	0081H

	COMP0_CON	1F88H	7CH	00E8H	3EH	00C8H	1FH	0088H

	COMP1_CON	1F8CH	7CH	00ECH	3EH	00CCH	1FH	008CH

	COMP0_TIME†	1F8AH	7CH	00EAH	3EH	00CAH	1FH	008AH
	COMP1_TIME†	1F8EH	7CH	00EEH	3EH	00CEH	1FH	008EH
	EPA_MASK†	1FA0H	7DH	00E0H	3EH	00E0H	1FH	00A0H
	EPA_MASK1	1FA4H	7DH	00E4H	3EH	00E4H	1FH	00A4H

	EPA_PEND†	1FA2H	7DH	00E2H	3EH	00E2H	1FH	00A2H
	EPA_PEND1	1FA6H	7DH	00E6H	3EH	00E6H	1FH	00A6H

	EPA0_CON	1F60H	7BH	00E0H	3DH	00E0H	1EH	00E0H

	EPA1_CON†	1F64H	7BH	00E4H	3DH	00E4H	1EH	00E4H
	EPA2_CON	1F68H	7BH	00E8H	3DH	00E8H	1EH	00E8H

	EPA3_CON†	1F6CH	7BH	00ECH	3DH	00ECH	1EH	00ECH
	EPA8_CON	1F80H	7CH	00E0H	3EH	00C0H	1FH	0080H

	EPA9_CON	1F84H	7CH	00E4H	3EH	00C4H	1FH	0084H

	EPA9_TIME†	1F86H	7CH	00E6H	3EH	00C6H	1FH	0086H
	EPA0_TIME†	1F62H	7BH	00E2H	3DH	00E2H	1EH	00E2H
	EPA1_TIME†	1F66H	7BH	00E6H	3DH	00E6H	1EH	00E6H

†Must be addressed as a word.

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Intel 87C196CB, 8XC196NT user manual Memory Partitions, byte Windows, Register Mnemonic, Location

Contents

87C196CB Supplement to 8XC196NT User’s Manual 87C196CB Supplement to 8XC196NT User’s Manual AugustOrder Number Copyright Intel Corporation, 1998 GUIDE TO THIS MANUAL CONTENTSCHAPTER CHAPTERCHAPTER SIGNAL DESCRIPTIONS87C196CB SUPPLEMENT SPECIAL OPERATING MODESInternal Clock Phases FIGURESCONTENTS Effect of Clock Mode on CLKOUT FrequencyPage FIGURES8XC196CB SUPPLEMENT 87C196CB 100-pin QFP PackageTABLES CONTENTSPage Page Guide to This Manual Page 1.1 MANUAL CONTENTS CHAPTER GUIDE TO THIS MANUAL1.2 RELATED DOCUMENTS Appendix A - Signal DescriptionsChapter 9 - Interfacing with External Memory Architectural Overview Page 2.1 DEVICE FEATURES CHAPTER ARCHITECTURAL OVERVIEW2.2 BLOCK DIAGRAM 2.3 INTERNAL TIMINGPage 16 MHz 8 MHz12 MHz 20 MHzFrequency Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyARCHITECTURAL OVERVIEW Input Frequency toPage Memory Partitions Page CHAPTER MEMORY PARTITIONS 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map AddressPorts 0, 1, 2, and 6 SFRs Timer 1, Timer 2, and EPA SFRsMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs SIO and SSIO SFRs87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs 1EDCH1ECCH MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued Message64-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs32-byte Window 128-byte WindowRegister RAM MEMORY PARTITIONSTable 3-6. Selecting a Window of the Upper Register File Locations87C196CB SUPPLEMENT MEMORY PARTITIONS Table 3-7. Selecting a Window of Upper Register RAM0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows MEMORY PARTITIONS Table 3-8. Windows ContinuedUpper Register File Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs 87C196CB SUPPLEMENTMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 64-byte Windows MEMORY PARTITIONS32-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page CHAPTER STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIESFigure 4-2. interrupt Pending 1 INTPEND1 Register 87C196CB SUPPLEMENTFigure 4-1. Interrupt Mask 1 INTMASK1 Register Standard VectorI/O Ports Page CHAPTER I/O PORTS 5.1 PORT 0 AND EPORTFigure 5-2. Extended Port I/O Direction EPDIR Register Figure 5-3. Extended Port Mode EPMODE Register87C196CB SUPPLEMENT EPDIRFigure 5-5. Extended Port Data Output EPREG Register I/O PORTSFigure 5-4. Extended Port Input EPPIN Register EPPINPage Analog-to-digital A/D Converter Page CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELS87C196CB SUPPLEMENT Figure 6-1. A/D Command ADCOMMAND RegisterADCOMMAND FunctionADRESULT Read ANALOG-TO-DIGITAL A/D CONVERTERFigure 6-2. A/D Result ADRESULT Register - Read Format FunctionPage CAN Serial Communications Controller Page CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.1 CAN FUNCTIONAL OVERVIEWPage CAN SERIAL COMMUNICATIONS CONTROLLER 7.2 CAN CONTROLLER SIGNALS AND REGISTERSTable 7-1. CAN Controller Signals Table 7-2. Control and Status Registers7.3 CAN CONTROLLER OPERATION 87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued7.3.1 Address Map 7.3.2 Message Objects7.3.2.1 Receive and Transmit Priorities Contents87C196CB SUPPLEMENT Table 7-4. Message Object Structure 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Table 7-7. Extended Message Frame7.3.4 Error Detection and Management Logic 7.3.5 Bit Timing SymbolDefinition Table 7-9. CAN Controller Bit Time Segments CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-5. A Bit Time as Implemented in the CAN Controller t SYNC87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations whereTable 7-10 defines the bit timing relationships of the CAN controller Table 7-10. Bit Timing Relationships7.4 CONFIGURING THE CAN CONTROLLER 7.4.1 Programming the CAN Control CANCON RegisterThis bit globally enables and disables interrupts error, status-change, and 87C196CB SUPPLEMENTFigure 7-6. CAN Control CANCON Register Continued 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register UnchangedFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register 7.4.3 Programming the Bit Timing 1 CANBTIME1 Register87C196CB SUPPLEMENT TSEG2Requirement 7.4.4 Programming a Message Acceptance FilterBit Time CommentsCANSGMSK 87C196CB SUPPLEMENTFigure 7-9. CAN Standard Global Mask CANSGMSK Register 87C196CBCANEGMSK CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-10. CAN Extended Global Mask CANEGMSK Register 87C196CB7.5 CONFIGURING MESSAGE OBJECTS 87C196CB SUPPLEMENTFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 7.5.2 Programming the Message Object Identifier 87C196CB SUPPLEMENTFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.3 Programming the Message Object Control Registers 7.5.4 Programming the Message Object DataAccess Type 87C196CB SUPPLEMENT Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 RegisterProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 RegisterCAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 RegistersFunction 7.6 ENABLING THE CAN INTERRUPTS CANCON Continued 87C196CB SUPPLEMENTFigure 7-17. CAN Control CANCON Register Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-20. CAN Status CANSTAT Register87C196CB SUPPLEMENT Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register7.8 FLOW DIAGRAMS Register MnemonicFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow Process message contents87C196CB SUPPLEMENT A2594-01CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-23. Receiving a Message for Message Object 15 - CPU FlowRestart Process Received frame with 87C196CB SUPPLEMENTFigure 7-24. Receiving a Message - CAN Controller Flow same identifer as thisCAN SERIAL COMMUNICATIONS CONTROLLER Power UpUpdate Figure 7-25. Transmitting a Message - CPU FlowReceived remote frame 87C196CB SUPPLEMENTFigure 7-26. Transmitting a Message - CAN Controller Flow with same identifer as7.9.2 Software Initialization 7.9.1 Hardware Reset7.9 DESIGN CONSIDERATIONS 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page CHAPTER SPECIAL OPERATING MODES 8.1 CLOCK CIRCUITRYFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page 9.1 ADDRESS PINS CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY9.2 BUS TIMING MODES T RLDV = 1t 87C196CB SUPPLEMENTFigure 9-1. Modes 0 and 3 Timings T AVDV = 3t= always enabled Figure 9-2. Chip Configuration 1 CCR1 Registerno direct access † INTERFACING WITH EXTERNAL MEMORYCCR1 Continued Figure 9-2. Chip Configuration 1 CCR1 Register Continued87C196CB SUPPLEMENT FunctionProgramming the Nonvolatile Memory Page 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory MapTable 10-3. Auto Programming Memory Map Figure 10-1. Auto Programming Circuit 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGPROGRAMMING THE NONVOLATILE MEMORY 74HC1410.4.1 Selecting Bank 0 FF2000-FF7FFFH 10.4.2 Selecting Bank 1 FF8000-FFFFFFHSerial Port Programming Mode Signal Descriptions Page APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALSxx87C196CB 87C196CB SupplementFigure A-1. 87C196CB 84-pin PLCC Package View of component asFigure A-2. 87C196CB 100-pin QFP Package A.2 SIGNAL DESCRIPTIONSSIGNAL DESCRIPTIONS xx87C196CBTable A-3. Signal Descriptions 87C196CB SupplementTable A-2. Description of Columns of Table A-3 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions Continuedread or write. AINC# is sampled after each location is programmed or dumped Table A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementA-10 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-11 Table A-3. Signal Descriptions Continued 87C196CB SupplementA-12 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-13 Table A-4. Definition of Status Symbols A.3 DEFAULT CONDITIONSTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-5. 87C196CB Pin Status ContinuedA-15 Page Glossary Page GLOSSARY channel-to-channel matching error transfer function of an A/D convertertwo adjacent code transitions on the A/D converter characteristicconversion result. Differential nonlinearity is a earity errorsSee off-isolation code widthare to be serviced by interrupt service routines that The characteristic of an ideal A/D converter. An ideallinearity errors. Quantizing error is the only error starting address of an interrupt service routineSee interrupt service routine See differential nonlinearity and nonlinearitylinearity errors OTPROM. Consult the Automotive Products or terminal-based characteristic from the correserviced by interrupt service routines that you Embedded Microcontrollers databook to determinedirectly to the interrupt service routine when See PTS control blockprioritized interrupt quantizing error transitions from different actual characteristics takenideal A/D converter repeatability errorSuccessive approximation register. A component of the A/D convertersample delay characteristic of the A/D converter service routinescaled to remove zero-offset error and full-scale interrupt controller for processing by an interruptisolation, and VCC rejection errors process quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity characteristicPage Index Page INDEX 87C196CB SUPPLEMENT Index-2