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Intel 8XC196NT, 87C196CB user manual

Models: 8XC196NT 87C196CB

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Intel 8XC196NT, 87C196CB user manual

Contents

87C196CB Supplement to 8XC196NT User’s Manual Order Number 87C196CB Supplement to 8XC196NT User’s ManualAugust Copyright Intel Corporation, 1998 CHAPTER CONTENTSGUIDE TO THIS MANUAL CHAPTER87C196CB SUPPLEMENT SIGNAL DESCRIPTIONSCHAPTER SPECIAL OPERATING MODESCONTENTS FIGURESInternal Clock Phases Effect of Clock Mode on CLKOUT Frequency8XC196CB SUPPLEMENT FIGURESPage 87C196CB 100-pin QFP PackagePage TABLESCONTENTS Page Guide to This Manual Page CHAPTER GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTSChapter 9 - Interfacing with External Memory 1.2 RELATED DOCUMENTSAppendix A - Signal Descriptions Architectural Overview Page CHAPTER ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES2.3 INTERNAL TIMING 2.2 BLOCK DIAGRAMPage 12 MHz 8 MHz16 MHz 20 MHzARCHITECTURAL OVERVIEW Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyFrequency Input Frequency toPage Memory Partitions Page 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING CHAPTER MEMORY PARTITIONSAddress 87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory MapMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs Timer 1, Timer 2, and EPA SFRsPorts 0, 1, 2, and 6 SFRs SIO and SSIO SFRs1ECCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1EDCH Message MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued32-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs64-byte Window 128-byte WindowTable 3-6. Selecting a Window of the Upper Register File MEMORY PARTITIONSRegister RAM Locations87C196CB SUPPLEMENT 0DE0-0DFFH MEMORY PARTITIONSTable 3-7. Selecting a Window of Upper Register RAM 87C196CB SUPPLEMENT Table 3-8. Windows Upper Register File MEMORY PARTITIONSTable 3-8. Windows Continued 87C196CB SUPPLEMENT Table 3-9. WSR Settings and Direct Addresses for Windowable SFRsMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 32-byte Windows MEMORY PARTITIONS64-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES CHAPTER STANDARD AND PTS INTERRUPTSFigure 4-1. Interrupt Mask 1 INTMASK1 Register 87C196CB SUPPLEMENTFigure 4-2. interrupt Pending 1 INTPEND1 Register Standard VectorI/O Ports Page 5.1 PORT 0 AND EPORT CHAPTER I/O PORTS87C196CB SUPPLEMENT Figure 5-3. Extended Port Mode EPMODE RegisterFigure 5-2. Extended Port I/O Direction EPDIR Register EPDIRFigure 5-4. Extended Port Input EPPIN Register I/O PORTSFigure 5-5. Extended Port Data Output EPREG Register EPPINPage Analog-to-digital A/D Converter Page 6.1 ADDITIONAL A/D INPUT CHANNELS CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTERADCOMMAND Figure 6-1. A/D Command ADCOMMAND Register87C196CB SUPPLEMENT FunctionFigure 6-2. A/D Result ADRESULT Register - Read Format ANALOG-TO-DIGITAL A/D CONVERTERADRESULT Read FunctionPage CAN Serial Communications Controller Page 7.1 CAN FUNCTIONAL OVERVIEW CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLERPage Table 7-1. CAN Controller Signals 7.2 CAN CONTROLLER SIGNALS AND REGISTERSCAN SERIAL COMMUNICATIONS CONTROLLER Table 7-2. Control and Status Registers87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued 7.3 CAN CONTROLLER OPERATION7.3.2 Message Objects 7.3.1 Address Map87C196CB SUPPLEMENT Table 7-4. Message Object Structure Contents7.3.2.1 Receive and Transmit Priorities 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames Table 7-7. Extended Message Frame 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame7.3.4 Error Detection and Management Logic Definition 7.3.5 Bit TimingSymbol Figure 7-5. A Bit Time as Implemented in the CAN Controller CAN SERIAL COMMUNICATIONS CONTROLLERTable 7-9. CAN Controller Bit Time Segments t SYNCTable 7-10 defines the bit timing relationships of the CAN controller where87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations Table 7-10. Bit Timing Relationships7.4.1 Programming the CAN Control CANCON Register 7.4 CONFIGURING THE CAN CONTROLLERFigure 7-6. CAN Control CANCON Register Continued This bit globally enables and disables interrupts error, status-change, and87C196CB SUPPLEMENT Unchanged 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register87C196CB SUPPLEMENT 7.4.3 Programming the Bit Timing 1 CANBTIME1 RegisterFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register TSEG2Bit Time 7.4.4 Programming a Message Acceptance FilterRequirement CommentsFigure 7-9. CAN Standard Global Mask CANSGMSK Register 87C196CB SUPPLEMENTCANSGMSK 87C196CBFigure 7-10. CAN Extended Global Mask CANEGMSK Register CAN SERIAL COMMUNICATIONS CONTROLLERCANEGMSK 87C196CBFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5 CONFIGURING MESSAGE OBJECTS87C196CB SUPPLEMENT 7.5.1 Specifying a Message Object’s Configuration Figure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.2 Programming the Message Object Identifier87C196CB SUPPLEMENT Access Type 7.5.3 Programming the Message Object Control Registers7.5.4 Programming the Message Object Data Program the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending 87C196CB SUPPLEMENTFigure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 Register 87C196CB SUPPLEMENTCAN SERIAL COMMUNICATIONS CONTROLLER Function 87C196CB SUPPLEMENTFigure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 7.6 ENABLING THE CAN INTERRUPTS Figure 7-17. CAN Control CANCON Register Continued 87C196CB SUPPLEMENTCANCON Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS Figure 7-20. CAN Status CANSTAT Register CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTRegister Mnemonic 7.8 FLOW DIAGRAMS87C196CB SUPPLEMENT Process message contentsFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow A2594-01Restart Process CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-23. Receiving a Message for Message Object 15 - CPU Flow Figure 7-24. Receiving a Message - CAN Controller Flow 87C196CB SUPPLEMENTReceived frame with same identifer as thisUpdate Power UpCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-25. Transmitting a Message - CPU FlowFigure 7-26. Transmitting a Message - CAN Controller Flow 87C196CB SUPPLEMENTReceived remote frame with same identifer as7.9 DESIGN CONSIDERATIONS 7.9.1 Hardware Reset7.9.2 Software Initialization 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page Figure 8-1. Clock Circuitry CHAPTER SPECIAL OPERATING MODES8.1 CLOCK CIRCUITRY Page Interfacing with External Memory Page 9.2 BUS TIMING MODES 9.1 ADDRESS PINSCHAPTER 9 INTERFACING WITH EXTERNAL MEMORY Figure 9-1. Modes 0 and 3 Timings 87C196CB SUPPLEMENTT RLDV = 1t T AVDV = 3tno direct access † Figure 9-2. Chip Configuration 1 CCR1 Register= always enabled INTERFACING WITH EXTERNAL MEMORY87C196CB SUPPLEMENT Figure 9-2. Chip Configuration 1 CCR1 Register ContinuedCCR1 Continued FunctionProgramming the Nonvolatile Memory Page 10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODECHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY Table 10-3. Auto Programming Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map PROGRAMMING THE NONVOLATILE MEMORY 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGFigure 10-1. Auto Programming Circuit 74HC14Serial Port Programming Mode 10.4.1 Selecting Bank 0 FF2000-FF7FFFH10.4.2 Selecting Bank 1 FF8000-FFFFFFH Signal Descriptions Page A.1 FUNCTIONAL GROUPINGS OF SIGNALS APPENDIX A SIGNAL DESCRIPTIONSFigure A-1. 87C196CB 84-pin PLCC Package 87C196CB Supplementxx87C196CB View of component asSIGNAL DESCRIPTIONS A.2 SIGNAL DESCRIPTIONSFigure A-2. 87C196CB 100-pin QFP Package xx87C196CBTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions87C196CB Supplement read or write. AINC# is sampled after each location is programmed or dumped SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued 87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONS87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-10 Table A-3. Signal Descriptions Continued87C196CB Supplement A-11 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued A-12 Table A-3. Signal Descriptions Continued87C196CB Supplement A-13 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued Table A-3. Signal Descriptions Continued A.3 DEFAULT CONDITIONSTable A-4. Definition of Status Symbols 87C196CB SupplementA-15 SIGNAL DESCRIPTIONSTable A-5. 87C196CB Pin Status Continued Page Glossary Page GLOSSARY two adjacent code transitions on the A/D converter transfer function of an A/D converterchannel-to-channel matching error characteristicSee off-isolation earity errorsconversion result. Differential nonlinearity is a code widthlinearity errors. Quantizing error is the only error The characteristic of an ideal A/D converter. An idealare to be serviced by interrupt service routines that starting address of an interrupt service routinelinearity errors See interrupt service routineSee differential nonlinearity and nonlinearity serviced by interrupt service routines that you terminal-based characteristic from the correOTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determineprioritized interrupt directly to the interrupt service routine whenSee PTS control block ideal A/D converter transitions from different actual characteristics takenquantizing error repeatability errorsample delay Successive approximation register. A component ofthe A/D converter scaled to remove zero-offset error and full-scale service routinecharacteristic of the A/D converter interrupt controller for processing by an interrupterror, differential nonlinearity, and nonlinearity process quantizing error, zero-offset error, full-scaleisolation, and VCC rejection errors characteristicPage Index Page INDEX Index-2 87C196CB SUPPLEMENT