Intel 87C196CB Sample delay uncertainty, Sample time uncertainty, Sample window, Set

	GLOSSARY
sample delay	The time period between the time that A/D converter
	receives the “start conversion” signal and the time
	that the sample capacitor is connected to the selected
	channel.
sample delay uncertainty	The variation in the sample delay.
sample time	The period of time that the sample window is open.
	(That is, the length of time that the input channel is
	actually connected to the sample capacitor.)
sample time uncertainty	The variation in the sample time.
sample window	The period of time that begins when the sample
	capacitor is attached to a selected channel of an A/D
	converter and ends when the sample capacitor is
	disconnected from the selected channel.
sampled inputs	All input pins, with the exception of RESET#, are
	sampled inputs. The input pin is sampled one state
	time before the read buffer is enabled. Sampling
	occurs during PH1 (while CLKOUT is low) and
	resolves the value (high or low) of the pin before it is
	presented to the internal bus. If the pin value changes
	during the sample time, the new value may or may not
	be recorded during the read.
	RESET# is a level-sensitive input. EXTINT is
	normally a sampled input; however, the powerdown
	circuitry uses EXTINT as a level-sensitive input
	during powerdown mode.
SAR	Successive approximation register. A component of
	the A/D converter.
set	The “1” value of a bit or the act of giving it a “1”
	value. See also clear.
SFR	Special-function register.
SHORT-INTEGER	An 8-bit, signed variable with values from –2 7
	through +27–1.
sign extension	A method for converting data to a larger format by
	filling the upper bit positions with the value of the
	sign. This conversion preserves the positive or
	negative value of signed integers.
sink current	Current flowing into a device to ground. Always a
	positive value.
	Glossary-9