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Intel 8XC196NT, 87C196CB user manual byte Windows

Models: 8XC196NT 87C196CB

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Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs (Continued)

			32-byte Windows		64-byte Windows		128-byte Windows
	Register Mnemonic	Memory	(00E0–00FFH)		(00C0–00FFH)		(0080–00FFH)
		Memory
		Location	WSR	Direct	WSR	Direct	WSR	Direct
		Location

				Address		Address		Address
				Address		Address		Address

	EPA2_TIME†	1F6AH	7BH	00EAH	3DH	00EAH	1EH	00EAH
	EPA3_TIME†	1F6EH	7BH	00EEH	3DH	00EEH	1EH	00EEH
	EPA8_TIME†	1F82H	7CH	00E2H	3EH	00C2H	1FH	0082H
	EPA9_TIME†	1F86H	7CH	00E6H	3EH	00C6H	1FH	0086H
	EPAIPV	1FA8H	7DH	00E8H	3EH	00E8H	1FH	00A8H

	P1_DIR	1FD2H	7EH	00F2H	3FH	00D2H	1FH	00D2H

	P2_DIR	1FCBH	7EH	00EBH	3FH	00CBH	1FH	00CBH

	P6_DIR	1FD3H	7EH	00F3H	3FH	00D3H	1FH	00D3H

	P1_MODE	1FD0H	7EH	00F0H	3FH	00D0H	1FH	00D0H

	P2_MODE	1FC9H	7EH	00E9H	3FH	00C9H	1FH	00C9H

	P6_MODE	1FD1H	7EH	00F1H	3FH	00D1H	1FH	00D1H

	P0_PIN	1FDAH	7EH	00FAH	3FH	00DAH	1FH	00DAH

	P1_PIN	1FD6H	7EH	00F6H	3FH	00D6H	1FH	00D6H

	P2_PIN	1FCFH	7EH	00EFH	3FH	00CFH	1FH	00CFH

	P6_PIN	1FD7H	7EH	00F7H	3FH	00D7H	1FH	00D7H

	P1_REG	1FD4H	7EH	00F4H	3FH	00D4H	1FH	00D4H

	P2_REG	1FCDH	7EH	00EDH	3FH	00CDH	1FH	00CDH

	P6_REG	1FD5H	7EH	00F5H	3FH	00D5H	1FH	00D5H

	SBUF_RX	1FB8H	7DH	00F8H	3EH	00F8H	1FH	00B8H

	SBUF_TX	1FBAH	7DH	00FAH	3EH	00FAH	1FH	00BAH

	SP_BAUD†	1FBCH	7DH	00FCH	3EH	00FCH	1FH	00BCH
	SP_CON	1FBBH	7DH	00FBH	3EH	00FBH	1FH	00BBH

	SP_STATUS	1FB9H	7DH	00F9H	3EH	00F9H	1FH	00B9H

	SSIO_BAUD	1FB4H	7DH	00F4H	3EH	00F4H	1FH	00B4H

	SSIO0_BUF	1FB0H	7DH	00F0H	3EH	00F0H	1FH	00B0H

	SSIO1_BUF	1FB2H	7DH	00F2H	3EH	00F2H	1FH	00B2H

	SSIO0_CON	1FB1H	7DH	00F1H	3EH	00F1H	1FH	00B1H

	SSIO1_CON	1FB3H	7DH	00F3H	3EH	00F3H	1FH	00B3H

	T1CONTROL	1F98H	7CH	00F8H	3EH	00D8H	1FH	0098H

	T2CONTROL	1F9CH	7CH	00FCH	3EH	00DCH	1FH	009CH

	TIMER1†	1F9AH	7CH	00FAH	3EH	00DAH	1FH	009AH
	TIMER2†	1F9EH	7CH	00FEH	3EH	00DEH	1FH	009EH

†Must be addressed as a word.

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Intel 8XC196NT, 87C196CB user manual byte Windows

Contents

87C196CB Supplement to 8XC196NT User’s Manual August 87C196CB Supplement to 8XC196NT User’s ManualOrder Number Copyright Intel Corporation, 1998 CHAPTER CONTENTSCHAPTER GUIDE TO THIS MANUALSPECIAL OPERATING MODES SIGNAL DESCRIPTIONS87C196CB SUPPLEMENT CHAPTEREffect of Clock Mode on CLKOUT Frequency FIGURESCONTENTS Internal Clock Phases87C196CB 100-pin QFP Package FIGURES8XC196CB SUPPLEMENT PageCONTENTS TABLESPage Page Guide to This Manual Page CHAPTER GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTSAppendix A - Signal Descriptions 1.2 RELATED DOCUMENTSChapter 9 - Interfacing with External Memory Architectural Overview Page CHAPTER ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES2.3 INTERNAL TIMING 2.2 BLOCK DIAGRAMPage 20 MHz 8 MHz12 MHz 16 MHzInput Frequency to Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyARCHITECTURAL OVERVIEW FrequencyPage Memory Partitions Page 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING CHAPTER MEMORY PARTITIONSAddress 87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory MapSIO and SSIO SFRs Timer 1, Timer 2, and EPA SFRsMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs Ports 0, 1, 2, and 6 SFRs1EDCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1ECCH Message MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued128-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs32-byte Window 64-byte WindowLocations MEMORY PARTITIONSTable 3-6. Selecting a Window of the Upper Register File Register RAM87C196CB SUPPLEMENT Table 3-7. Selecting a Window of Upper Register RAM MEMORY PARTITIONS0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows Table 3-8. Windows Continued MEMORY PARTITIONSUpper Register File 87C196CB SUPPLEMENT Table 3-9. WSR Settings and Direct Addresses for Windowable SFRsMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 128-byte Windows MEMORY PARTITIONS32-byte Windows 64-byte Windows32-byte Windows Standard and PTS Interrupts Page 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES CHAPTER STANDARD AND PTS INTERRUPTSStandard Vector 87C196CB SUPPLEMENTFigure 4-1. Interrupt Mask 1 INTMASK1 Register Figure 4-2. interrupt Pending 1 INTPEND1 RegisterI/O Ports Page 5.1 PORT 0 AND EPORT CHAPTER I/O PORTSEPDIR Figure 5-3. Extended Port Mode EPMODE Register87C196CB SUPPLEMENT Figure 5-2. Extended Port I/O Direction EPDIR RegisterEPPIN I/O PORTSFigure 5-4. Extended Port Input EPPIN Register Figure 5-5. Extended Port Data Output EPREG RegisterPage Analog-to-digital A/D Converter Page 6.1 ADDITIONAL A/D INPUT CHANNELS CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTERFunction Figure 6-1. A/D Command ADCOMMAND RegisterADCOMMAND 87C196CB SUPPLEMENTFunction ANALOG-TO-DIGITAL A/D CONVERTERFigure 6-2. A/D Result ADRESULT Register - Read Format ADRESULT ReadPage CAN Serial Communications Controller Page 7.1 CAN FUNCTIONAL OVERVIEW CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLERPage Table 7-2. Control and Status Registers 7.2 CAN CONTROLLER SIGNALS AND REGISTERSTable 7-1. CAN Controller Signals CAN SERIAL COMMUNICATIONS CONTROLLER87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued 7.3 CAN CONTROLLER OPERATION7.3.2 Message Objects 7.3.1 Address Map7.3.2.2 Message Acceptance Filtering Contents87C196CB SUPPLEMENT Table 7-4. Message Object Structure 7.3.2.1 Receive and Transmit Priorities7.3.3 Message Frames Table 7-7. Extended Message Frame 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame7.3.4 Error Detection and Management Logic Symbol 7.3.5 Bit TimingDefinition t SYNC CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-5. A Bit Time as Implemented in the CAN Controller Table 7-9. CAN Controller Bit Time SegmentsTable 7-10. Bit Timing Relationships whereTable 7-10 defines the bit timing relationships of the CAN controller 87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations7.4.1 Programming the CAN Control CANCON Register 7.4 CONFIGURING THE CAN CONTROLLER87C196CB SUPPLEMENT This bit globally enables and disables interrupts error, status-change, andFigure 7-6. CAN Control CANCON Register Continued Unchanged 7.4.2 Programming the Bit Timing 0 CANBTIME0 RegisterTSEG2 7.4.3 Programming the Bit Timing 1 CANBTIME1 Register87C196CB SUPPLEMENT Figure 7-8. CAN Bit Timing 1 CANBTIME1 RegisterComments 7.4.4 Programming a Message Acceptance FilterBit Time Requirement87C196CB 87C196CB SUPPLEMENTFigure 7-9. CAN Standard Global Mask CANSGMSK Register CANSGMSK87C196CB CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-10. CAN Extended Global Mask CANEGMSK Register CANEGMSK87C196CB SUPPLEMENT 7.5 CONFIGURING MESSAGE OBJECTSFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 87C196CB SUPPLEMENT 7.5.2 Programming the Message Object IdentifierFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.4 Programming the Message Object Data 7.5.3 Programming the Message Object Control RegistersAccess Type Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 Register 87C196CB SUPPLEMENTCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 87C196CB SUPPLEMENTFunction 7.6 ENABLING THE CAN INTERRUPTS 87C196CB 87C196CB SUPPLEMENTFigure 7-17. CAN Control CANCON Register Continued CANCON ContinuedWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS Figure 7-20. CAN Status CANSTAT Register CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTRegister Mnemonic 7.8 FLOW DIAGRAMSA2594-01 Process message contents87C196CB SUPPLEMENT Figure 7-22. Receiving a Message for Message Objects 1-14 - CPU FlowFigure 7-23. Receiving a Message for Message Object 15 - CPU Flow CAN SERIAL COMMUNICATIONS CONTROLLERRestart Process same identifer as this 87C196CB SUPPLEMENTFigure 7-24. Receiving a Message - CAN Controller Flow Received frame withFigure 7-25. Transmitting a Message - CPU Flow Power UpUpdate CAN SERIAL COMMUNICATIONS CONTROLLERwith same identifer as 87C196CB SUPPLEMENTFigure 7-26. Transmitting a Message - CAN Controller Flow Received remote frame7.9.3 Bus-off State 7.9.1 Hardware Reset7.9 DESIGN CONSIDERATIONS 7.9.2 Software InitializationThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page 8.1 CLOCK CIRCUITRY CHAPTER SPECIAL OPERATING MODESFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY 9.1 ADDRESS PINS9.2 BUS TIMING MODES T AVDV = 3t 87C196CB SUPPLEMENTFigure 9-1. Modes 0 and 3 Timings T RLDV = 1tINTERFACING WITH EXTERNAL MEMORY Figure 9-2. Chip Configuration 1 CCR1 Registerno direct access † = always enabledFunction Figure 9-2. Chip Configuration 1 CCR1 Register Continued87C196CB SUPPLEMENT CCR1 ContinuedProgramming the Nonvolatile Memory Page CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMINGTable 10-3. Auto Programming Memory Map 74HC14 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGPROGRAMMING THE NONVOLATILE MEMORY Figure 10-1. Auto Programming Circuit10.4.2 Selecting Bank 1 FF8000-FFFFFFH 10.4.1 Selecting Bank 0 FF2000-FF7FFFHSerial Port Programming Mode Signal Descriptions Page A.1 FUNCTIONAL GROUPINGS OF SIGNALS APPENDIX A SIGNAL DESCRIPTIONSView of component as 87C196CB SupplementFigure A-1. 87C196CB 84-pin PLCC Package xx87C196CBxx87C196CB A.2 SIGNAL DESCRIPTIONSSIGNAL DESCRIPTIONS Figure A-2. 87C196CB 100-pin QFP Package87C196CB Supplement Table A-3. Signal DescriptionsTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSread or write. AINC# is sampled after each location is programmed or dumped 87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONS87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONS87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-10 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-11 87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-12 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-13 87C196CB Supplement A.3 DEFAULT CONDITIONSTable A-3. Signal Descriptions Continued Table A-4. Definition of Status SymbolsTable A-5. 87C196CB Pin Status Continued SIGNAL DESCRIPTIONSA-15 Page Glossary Page GLOSSARY characteristic transfer function of an A/D convertertwo adjacent code transitions on the A/D converter channel-to-channel matching errorcode width earity errorsSee off-isolation conversion result. Differential nonlinearity is astarting address of an interrupt service routine The characteristic of an ideal A/D converter. An ideallinearity errors. Quantizing error is the only error are to be serviced by interrupt service routines thatSee differential nonlinearity and nonlinearity See interrupt service routinelinearity errors Embedded Microcontrollers databook to determine terminal-based characteristic from the correserviced by interrupt service routines that you OTPROM. Consult the Automotive Products orSee PTS control block directly to the interrupt service routine whenprioritized interrupt repeatability error transitions from different actual characteristics takenideal A/D converter quantizing errorthe A/D converter Successive approximation register. A component ofsample delay interrupt controller for processing by an interrupt service routinescaled to remove zero-offset error and full-scale characteristic of the A/D convertercharacteristic process quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity isolation, and VCC rejection errorsPage Index Page INDEX Index-2 87C196CB SUPPLEMENT