87C196CB Supplement to 8XC196NT User’s Manual
Order Number
87C196CB Supplement to 8XC196NT User’s Manual
August
Copyright Intel Corporation, 1998
GUIDE TO THIS MANUAL
CONTENTS
CHAPTER
CHAPTER
CHAPTER
SIGNAL DESCRIPTIONS
87C196CB SUPPLEMENT
SPECIAL OPERATING MODES
Internal Clock Phases
FIGURES
CONTENTS
Effect of Clock Mode on CLKOUT Frequency
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FIGURES
8XC196CB SUPPLEMENT
87C196CB 100-pin QFP Package
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TABLES
CONTENTS
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Guide to This Manual
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1.1 MANUAL CONTENTS
CHAPTER GUIDE TO THIS MANUAL
Chapter 9 - Interfacing with External Memory
1.2 RELATED DOCUMENTS
Appendix A - Signal Descriptions
Architectural Overview
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2.1 DEVICE FEATURES
CHAPTER ARCHITECTURAL OVERVIEW
2.2 BLOCK DIAGRAM
2.3 INTERNAL TIMING
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16 MHz
8 MHz
12 MHz
20 MHz
Frequency
Figure 2-4. Effect of Clock Mode on CLKOUT Frequency
ARCHITECTURAL OVERVIEW
Input Frequency to
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Memory Partitions
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CHAPTER MEMORY PARTITIONS
3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING
87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map
Address
Ports 0, 1, 2, and 6 SFRs
Timer 1, Timer 2, and EPA SFRs
MEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs
SIO and SSIO SFRs
1ECCH
87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs
1EDCH
MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued
Message
64-byte Window
87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs
32-byte Window
128-byte Window
Register RAM
MEMORY PARTITIONS
Table 3-6. Selecting a Window of the Upper Register File
Locations
87C196CB SUPPLEMENT
0DE0-0DFFH
MEMORY PARTITIONS
Table 3-7. Selecting a Window of Upper Register RAM
87C196CB SUPPLEMENT Table 3-8. Windows
Upper Register File
MEMORY PARTITIONS
Table 3-8. Windows Continued
Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs
87C196CB SUPPLEMENT
MEMORY PARTITIONS
87C196CB SUPPLEMENT
MEMORY PARTITIONS
87C196CB SUPPLEMENT
MEMORY PARTITIONS
87C196CB SUPPLEMENT
64-byte Windows
MEMORY PARTITIONS
32-byte Windows
128-byte Windows
32-byte Windows
Standard and PTS Interrupts
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CHAPTER STANDARD AND PTS INTERRUPTS
4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES
Figure 4-2. interrupt Pending 1 INTPEND1 Register
87C196CB SUPPLEMENT
Figure 4-1. Interrupt Mask 1 INTMASK1 Register
Standard Vector
I/O Ports
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CHAPTER I/O PORTS
5.1 PORT 0 AND EPORT
Figure 5-2. Extended Port I/O Direction EPDIR Register
Figure 5-3. Extended Port Mode EPMODE Register
87C196CB SUPPLEMENT
EPDIR
Figure 5-5. Extended Port Data Output EPREG Register
I/O PORTS
Figure 5-4. Extended Port Input EPPIN Register
EPPIN
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Analog-to-digital A/D Converter
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CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER
6.1 ADDITIONAL A/D INPUT CHANNELS
87C196CB SUPPLEMENT
Figure 6-1. A/D Command ADCOMMAND Register
ADCOMMAND
Function
ADRESULT Read
ANALOG-TO-DIGITAL A/D CONVERTER
Figure 6-2. A/D Result ADRESULT Register - Read Format
Function
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CAN Serial Communications Controller
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CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER
7.1 CAN FUNCTIONAL OVERVIEW
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CAN SERIAL COMMUNICATIONS CONTROLLER
7.2 CAN CONTROLLER SIGNALS AND REGISTERS
Table 7-1. CAN Controller Signals
Table 7-2. Control and Status Registers
7.3 CAN CONTROLLER OPERATION
87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued
7.3.1 Address Map
7.3.2 Message Objects
7.3.2.1 Receive and Transmit Priorities
Contents
87C196CB SUPPLEMENT Table 7-4. Message Object Structure
7.3.2.2 Message Acceptance Filtering
7.3.3 Message Frames
87C196CB SUPPLEMENT Table 7-6. Standard Message Frame
Table 7-7. Extended Message Frame
7.3.4 Error Detection and Management Logic
Definition
7.3.5 Bit Timing
Symbol
Table 7-9. CAN Controller Bit Time Segments
CAN SERIAL COMMUNICATIONS CONTROLLER
Figure 7-5. A Bit Time as Implemented in the CAN Controller
t SYNC
87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations
where
Table 7-10 defines the bit timing relationships of the CAN controller
Table 7-10. Bit Timing Relationships
7.4 CONFIGURING THE CAN CONTROLLER
7.4.1 Programming the CAN Control CANCON Register
Figure 7-6. CAN Control CANCON Register Continued
This bit globally enables and disables interrupts error, status-change, and
87C196CB SUPPLEMENT
7.4.2 Programming the Bit Timing 0 CANBTIME0 Register
Unchanged
Figure 7-8. CAN Bit Timing 1 CANBTIME1 Register
7.4.3 Programming the Bit Timing 1 CANBTIME1 Register
87C196CB SUPPLEMENT
TSEG2
Requirement
7.4.4 Programming a Message Acceptance Filter
Bit Time
Comments
CANSGMSK
87C196CB SUPPLEMENT
Figure 7-9. CAN Standard Global Mask CANSGMSK Register
87C196CB
CANEGMSK
CAN SERIAL COMMUNICATIONS CONTROLLER
Figure 7-10. CAN Extended Global Mask CANEGMSK Register
87C196CB
Figure 7-11. CAN Message 15 Mask CANMSK15 Register
7.5 CONFIGURING MESSAGE OBJECTS
87C196CB SUPPLEMENT
7.5.1 Specifying a Message Object’s Configuration
Figure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register
7.5.2 Programming the Message Object Identifier
87C196CB SUPPLEMENT
Access Type
7.5.3 Programming the Message Object Control Registers
7.5.4 Programming the Message Object Data
Program the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending
87C196CB SUPPLEMENT
Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register
CAN SERIAL COMMUNICATIONS CONTROLLER
87C196CB SUPPLEMENT
Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 Register
CAN SERIAL COMMUNICATIONS CONTROLLER
Function
87C196CB SUPPLEMENT
Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers
7.6 ENABLING THE CAN INTERRUPTS
CANCON Continued
87C196CB SUPPLEMENT
Figure 7-17. CAN Control CANCON Register Continued
87C196CB
When the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects
7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS
CAN SERIAL COMMUNICATIONS CONTROLLER
Figure 7-20. CAN Status CANSTAT Register
87C196CB SUPPLEMENT
Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register
7.8 FLOW DIAGRAMS
Register Mnemonic
Figure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow
Process message contents
87C196CB SUPPLEMENT
A2594-01
Restart Process
CAN SERIAL COMMUNICATIONS CONTROLLER
Figure 7-23. Receiving a Message for Message Object 15 - CPU Flow
Received frame with
87C196CB SUPPLEMENT
Figure 7-24. Receiving a Message - CAN Controller Flow
same identifer as this
CAN SERIAL COMMUNICATIONS CONTROLLER
Power Up
Update
Figure 7-25. Transmitting a Message - CPU Flow
Received remote frame
87C196CB SUPPLEMENT
Figure 7-26. Transmitting a Message - CAN Controller Flow
with same identifer as
7.9.2 Software Initialization
7.9.1 Hardware Reset
7.9 DESIGN CONSIDERATIONS
7.9.3 Bus-off State
The CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again
Special Operating Modes
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Figure 8-1. Clock Circuitry
CHAPTER SPECIAL OPERATING MODES
8.1 CLOCK CIRCUITRY
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Interfacing with External Memory
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9.2 BUS TIMING MODES
9.1 ADDRESS PINS
CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY
T RLDV = 1t
87C196CB SUPPLEMENT
Figure 9-1. Modes 0 and 3 Timings
T AVDV = 3t
= always enabled
Figure 9-2. Chip Configuration 1 CCR1 Register
no direct access †
INTERFACING WITH EXTERNAL MEMORY
CCR1 Continued
Figure 9-2. Chip Configuration 1 CCR1 Register Continued
87C196CB SUPPLEMENT
Function
Programming the Nonvolatile Memory
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10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES
10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE
CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY
Table 10-3. Auto Programming Memory Map
10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING
87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map
Figure 10-1. Auto Programming Circuit
10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMING
PROGRAMMING THE NONVOLATILE MEMORY
74HC14
Serial Port Programming Mode
10.4.1 Selecting Bank 0 FF2000-FF7FFFH
10.4.2 Selecting Bank 1 FF8000-FFFFFFH
Signal Descriptions
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APPENDIX A SIGNAL DESCRIPTIONS
A.1 FUNCTIONAL GROUPINGS OF SIGNALS
xx87C196CB
87C196CB Supplement
Figure A-1. 87C196CB 84-pin PLCC Package
View of component as
Figure A-2. 87C196CB 100-pin QFP Package
A.2 SIGNAL DESCRIPTIONS
SIGNAL DESCRIPTIONS
xx87C196CB
Table A-2. Description of Columns of Table A-3
Table A-3. Signal Descriptions
87C196CB Supplement
read or write. AINC# is sampled after each location is programmed or dumped
SIGNAL DESCRIPTIONS
Table A-3. Signal Descriptions Continued
Table A-3. Signal Descriptions Continued
87C196CB Supplement
SIGNAL DESCRIPTIONS
Table A-3. Signal Descriptions Continued
Table A-3. Signal Descriptions Continued
87C196CB Supplement
SIGNAL DESCRIPTIONS
Table A-3. Signal Descriptions Continued
A-10
Table A-3. Signal Descriptions Continued
87C196CB Supplement
A-11
SIGNAL DESCRIPTIONS
Table A-3. Signal Descriptions Continued
A-12
Table A-3. Signal Descriptions Continued
87C196CB Supplement
A-13
SIGNAL DESCRIPTIONS
Table A-3. Signal Descriptions Continued
Table A-4. Definition of Status Symbols
A.3 DEFAULT CONDITIONS
Table A-3. Signal Descriptions Continued
87C196CB Supplement
A-15
SIGNAL DESCRIPTIONS
Table A-5. 87C196CB Pin Status Continued
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Glossary
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GLOSSARY
channel-to-channel matching error
transfer function of an A/D converter
two adjacent code transitions on the A/D converter
characteristic
conversion result. Differential nonlinearity is a
earity errors
See off-isolation
code width
are to be serviced by interrupt service routines that
The characteristic of an ideal A/D converter. An ideal
linearity errors. Quantizing error is the only error
starting address of an interrupt service routine
linearity errors
See interrupt service routine
See differential nonlinearity and nonlinearity
OTPROM. Consult the Automotive Products or
terminal-based characteristic from the corre
serviced by interrupt service routines that you
Embedded Microcontrollers databook to determine
prioritized interrupt
directly to the interrupt service routine when
See PTS control block
quantizing error
transitions from different actual characteristics taken
ideal A/D converter
repeatability error
sample delay
Successive approximation register. A component of
the A/D converter
characteristic of the A/D converter
service routine
scaled to remove zero-offset error and full-scale
interrupt controller for processing by an interrupt
isolation, and VCC rejection errors
process quantizing error, zero-offset error, full-scale
error, differential nonlinearity, and nonlinearity
characteristic
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Index
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INDEX
87C196CB SUPPLEMENT
Index-2
