Intel 87C196CB, 8XC196NT user manual T2DIR, Txd, Wr#, Wrl#

SIGNAL DESCRIPTIONS

		Table A-3. Signal Descriptions (Continued)
Name	Type	Description
T2DIR	I	Timer 2 External Direction
		External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
		and decrements when it is low. Also used in conjunction with T2CLK for
		quadrature counting mode.
		T2DIR is multiplexed with P1.2 and EPA2.
TXCAN	O	Transmit
		This signal carries messages from the integrated CAN controller to other nodes
		on the CAN bus.
TXD	O	Transmit Serial Data
		In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode
		0, it is the serial clock output.
		TXD is multiplexed with P2.0 and PVER.
VCC	PWR	Digital Supply Voltage
		Connect each VCC pin to the digital supply voltage.
VPP	PWR	Programming Voltage
		During programming, the VPP pin is typically at +12.5 V (VPP voltage).
		Exceeding the maximum VPP voltage specification can damage the device.
		VPP also causes the device to exit powerdown mode when it is driven low for at
		least 50 ns. Use this method to exit powerdown only when using an external
		clock source because it enables the internal phase clocks, but not the internal
		oscillator.
VREF	PWR	Reference Voltage for the A/D Converter
		This pin also supplies operating voltage to both the analog portion of the A/D
		converter and the logic used to read port 0.
VSS, VSS1	GND	Digital Circuit Ground (Core Ground, Port Ground)
		Connect each VSS and VSS1 pin to ground through the lowest possible
		impedance path. VSS pins are connected to the core ground region of the micro-
		controller, while VSS1 pins are connected to the port ground region. (ANGND is
		connected to the analog ground region.) Separating the ground regions
		provides noise isolation.
WR#	O	Write†
		This active-low output indicates that an external write is occurring. This signal is
		asserted only during external memory writes.
		WR# is multiplexed with P5.2, SLPWR#, and WRL#.
		† The chip configuration register 0 (CCR0) determines whether this pin
		functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects
		WRL#.
WRH#	O	Write High†
		During 16-bit bus cycles, this active-low output signal is asserted for high-byte
		writes and word writes to external memory. During 8-bit bus cycles, WRH# is
		asserted for all write operations.
		WRH# is multiplexed with P5.5 and BHE#.
		† The chip configuration register 0 (CCR0) determines whether this pin
		functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
		WRH#.

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