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Intel 8XC196NT A.2 SIGNAL DESCRIPTIONS, Signal Descriptions, xx87C196CB, View of component as

Models: 8XC196NT 87C196CB

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SIGNAL DESCRIPTIONS

SIGNAL DESCRIPTIONS

EPORT.2 P3.1 / SLP1 / PBUS1 P3.2 / SLP2 / PBUS2 P3.3 / SLP3 / PBUS3 P3.4 / SLP4 / PBUS4 P3.5 / SLP5 / PBUS5 P3.6 / SLP6 / PBUS6 P3.7 / SLP7 / PBUS7	P4.0 / PBUS8 P4.1 / PBUS9 / P4.2 / PBUS10 / P4.3 / PBUS11 / P4.4 / PBUS12 / P4.5 / PBUS13 / P4.6 / PBUS14 / P4.7 / PBUS15 EPORT.0 EPORT.1
A18/ AD1/ AD2/ AD3/ AD4/ AD5/ AD6/ AD7/ V V AD8 AD9/ AD10 AD11 AD12 AD13 AD14 AD15 A16/ A17/
	/
	CC SS1

NC1 AD0 / P3.0 / SLP0 / PBUS02 RESET#3 NMI4 EA# 5 VSS1 6 NC 7 VCC 8 NC9

VSS 10

NC11

NC12

NC13

NC14 P2.0 / TXD / PVER15 P2.1 / RXD / PALE#16 P2.2 / EXTINT / PROG#17 P2.3 / BREQ#18 NC19

P2.4 / INTOUT# / AINC#20

P2.5 / HOLD#21

P2.6 / HLDA# / CPVER / ONCE#22

P2.7 / CLKOUT / PACT#23

VCC 24

VSS1 25

P0.0 / ACH026

P0.1 / ACH127

P0.2 / ACH228

P0.3 / ACH329

P0.4 / ACH4 / PMODE.030

100

31

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
	80	P5.7	/ BUSWIDTH
	79	P5.2	/ WR# / WRL# / SLPWR#
	78	P5.5	/ BHE# / WRH#
	77	P5.3	/ RD# / SLPRD#
	76	A20 / EPORT.4
	75	A21 / EPORT.5
	74	A22 / EPORT.6
	73	VPP
	72	A23 / EPORT.7
	71	P5.0	/ ADV# / ALE / SLPALE
xx87C196CB	70	P5.1	/ INST / SLPCS#
xx87C196CB	69	P5.6	/ READY
	68	P5.4	/ SLPINT
	67	A19 / EPORT.3
	66	NC
	65	VCC
	64	NC
View of component as	63	VSS1
mounted on PC board	62	VSS
mounted on PC board	61	NC
	60	RXCAN
	59	TXCAN
	58	XTAL1
	57	XTAL2
	56	NC
	55	P6.7	/ SD1
	54	P6.6	/ SC1
	53	P6.5	/ SD0
	52	P6.4	/ SC0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50	51	VCC

	REF CC SS1
P0.5 / ACH5 PMODE.1/ P0.6 / ACH6 PMODE.2/ P0.7 / ACH7 PMODE.3/ ANGND	V	V V P1.7 EPA7/ P1.6 EPA6/ P1.5 EPA5/ P1.4 EPA4/ P1.3 EPA3/ P1.2 / EPA2 T2DIR/ P1.1 EPA1/ P1.0 / EPA0 T2CLK/ P6.0 / EPA8 COMP0/ P6.1 / EPA9 COMP1/ P6.2 T1CLK/ P6.3 T1DIR/ PLLEN

		A3171-02

Figure A-2. 87C196CB 100-pin QFP Package

A.2 SIGNAL DESCRIPTIONS

Table A-2 defines the columns used in Table A-3, which describes the signals.

A-3

Image 124

Intel 8XC196NT A.2 SIGNAL DESCRIPTIONS, Signal Descriptions, Figure A-2. 87C196CB 100-pin QFP Package, xx87C196CB

Contents

87C196CB Supplement to 8XC196NT User’s Manual August 87C196CB Supplement to 8XC196NT User’s ManualOrder Number Copyright Intel Corporation, 1998 CONTENTS CHAPTERGUIDE TO THIS MANUAL CHAPTERSIGNAL DESCRIPTIONS 87C196CB SUPPLEMENTCHAPTER SPECIAL OPERATING MODESFIGURES CONTENTSInternal Clock Phases Effect of Clock Mode on CLKOUT FrequencyFIGURES 8XC196CB SUPPLEMENTPage 87C196CB 100-pin QFP PackageCONTENTS TABLESPage Page Guide to This Manual Page 1.1 MANUAL CONTENTS CHAPTER GUIDE TO THIS MANUALAppendix A - Signal Descriptions 1.2 RELATED DOCUMENTSChapter 9 - Interfacing with External Memory Architectural Overview Page 2.1 DEVICE FEATURES CHAPTER ARCHITECTURAL OVERVIEW2.2 BLOCK DIAGRAM 2.3 INTERNAL TIMINGPage 8 MHz 12 MHz16 MHz 20 MHzFigure 2-4. Effect of Clock Mode on CLKOUT Frequency ARCHITECTURAL OVERVIEWFrequency Input Frequency toPage Memory Partitions Page CHAPTER MEMORY PARTITIONS 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map AddressTimer 1, Timer 2, and EPA SFRs MEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRsPorts 0, 1, 2, and 6 SFRs SIO and SSIO SFRs1EDCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1ECCH MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued Message87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs 32-byte Window64-byte Window 128-byte WindowMEMORY PARTITIONS Table 3-6. Selecting a Window of the Upper Register FileRegister RAM Locations87C196CB SUPPLEMENT Table 3-7. Selecting a Window of Upper Register RAM MEMORY PARTITIONS0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows Table 3-8. Windows Continued MEMORY PARTITIONSUpper Register File Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs 87C196CB SUPPLEMENTMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 32-byte Windows64-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page CHAPTER STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES87C196CB SUPPLEMENT Figure 4-1. Interrupt Mask 1 INTMASK1 RegisterFigure 4-2. interrupt Pending 1 INTPEND1 Register Standard VectorI/O Ports Page CHAPTER I/O PORTS 5.1 PORT 0 AND EPORTFigure 5-3. Extended Port Mode EPMODE Register 87C196CB SUPPLEMENTFigure 5-2. Extended Port I/O Direction EPDIR Register EPDIRI/O PORTS Figure 5-4. Extended Port Input EPPIN RegisterFigure 5-5. Extended Port Data Output EPREG Register EPPINPage Analog-to-digital A/D Converter Page CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELSFigure 6-1. A/D Command ADCOMMAND Register ADCOMMAND87C196CB SUPPLEMENT FunctionANALOG-TO-DIGITAL A/D CONVERTER Figure 6-2. A/D Result ADRESULT Register - Read FormatADRESULT Read FunctionPage CAN Serial Communications Controller Page CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.1 CAN FUNCTIONAL OVERVIEWPage 7.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7-1. CAN Controller SignalsCAN SERIAL COMMUNICATIONS CONTROLLER Table 7-2. Control and Status Registers7.3 CAN CONTROLLER OPERATION 87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued7.3.1 Address Map 7.3.2 Message ObjectsContents 87C196CB SUPPLEMENT Table 7-4. Message Object Structure7.3.2.1 Receive and Transmit Priorities 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Table 7-7. Extended Message Frame7.3.4 Error Detection and Management Logic Symbol 7.3.5 Bit TimingDefinition CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-5. A Bit Time as Implemented in the CAN ControllerTable 7-9. CAN Controller Bit Time Segments t SYNCwhere Table 7-10 defines the bit timing relationships of the CAN controller87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations Table 7-10. Bit Timing Relationships7.4 CONFIGURING THE CAN CONTROLLER 7.4.1 Programming the CAN Control CANCON Register87C196CB SUPPLEMENT This bit globally enables and disables interrupts error, status-change, andFigure 7-6. CAN Control CANCON Register Continued 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register Unchanged7.4.3 Programming the Bit Timing 1 CANBTIME1 Register 87C196CB SUPPLEMENTFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register TSEG27.4.4 Programming a Message Acceptance Filter Bit TimeRequirement Comments87C196CB SUPPLEMENT Figure 7-9. CAN Standard Global Mask CANSGMSK RegisterCANSGMSK 87C196CBCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-10. CAN Extended Global Mask CANEGMSK RegisterCANEGMSK 87C196CB87C196CB SUPPLEMENT 7.5 CONFIGURING MESSAGE OBJECTSFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 87C196CB SUPPLEMENT 7.5.2 Programming the Message Object IdentifierFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.4 Programming the Message Object Data 7.5.3 Programming the Message Object Control RegistersAccess Type Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 RegisterCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 87C196CB SUPPLEMENTFunction 7.6 ENABLING THE CAN INTERRUPTS 87C196CB SUPPLEMENT Figure 7-17. CAN Control CANCON Register ContinuedCANCON Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-20. CAN Status CANSTAT Register87C196CB SUPPLEMENT Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register7.8 FLOW DIAGRAMS Register MnemonicProcess message contents 87C196CB SUPPLEMENTFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow A2594-01Figure 7-23. Receiving a Message for Message Object 15 - CPU Flow CAN SERIAL COMMUNICATIONS CONTROLLERRestart Process 87C196CB SUPPLEMENT Figure 7-24. Receiving a Message - CAN Controller FlowReceived frame with same identifer as thisPower Up UpdateCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-25. Transmitting a Message - CPU Flow87C196CB SUPPLEMENT Figure 7-26. Transmitting a Message - CAN Controller FlowReceived remote frame with same identifer as7.9.1 Hardware Reset 7.9 DESIGN CONSIDERATIONS7.9.2 Software Initialization 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page 8.1 CLOCK CIRCUITRY CHAPTER SPECIAL OPERATING MODESFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY 9.1 ADDRESS PINS9.2 BUS TIMING MODES 87C196CB SUPPLEMENT Figure 9-1. Modes 0 and 3 TimingsT RLDV = 1t T AVDV = 3tFigure 9-2. Chip Configuration 1 CCR1 Register no direct access †= always enabled INTERFACING WITH EXTERNAL MEMORYFigure 9-2. Chip Configuration 1 CCR1 Register Continued 87C196CB SUPPLEMENTCCR1 Continued FunctionProgramming the Nonvolatile Memory Page CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMINGTable 10-3. Auto Programming Memory Map 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMING PROGRAMMING THE NONVOLATILE MEMORYFigure 10-1. Auto Programming Circuit 74HC1410.4.2 Selecting Bank 1 FF8000-FFFFFFH 10.4.1 Selecting Bank 0 FF2000-FF7FFFHSerial Port Programming Mode Signal Descriptions Page APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALS87C196CB Supplement Figure A-1. 87C196CB 84-pin PLCC Packagexx87C196CB View of component asA.2 SIGNAL DESCRIPTIONS SIGNAL DESCRIPTIONSFigure A-2. 87C196CB 100-pin QFP Package xx87C196CB87C196CB Supplement Table A-3. Signal DescriptionsTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSread or write. AINC# is sampled after each location is programmed or dumped Table A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions Continued87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-10 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-11 87C196CB Supplement Table A-3. Signal Descriptions ContinuedA-12 Table A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSA-13 A.3 DEFAULT CONDITIONS Table A-3. Signal Descriptions ContinuedTable A-4. Definition of Status Symbols 87C196CB SupplementTable A-5. 87C196CB Pin Status Continued SIGNAL DESCRIPTIONSA-15 Page Glossary Page GLOSSARY transfer function of an A/D converter two adjacent code transitions on the A/D converterchannel-to-channel matching error characteristicearity errors See off-isolationconversion result. Differential nonlinearity is a code widthThe characteristic of an ideal A/D converter. An ideal linearity errors. Quantizing error is the only errorare to be serviced by interrupt service routines that starting address of an interrupt service routineSee differential nonlinearity and nonlinearity See interrupt service routinelinearity errors terminal-based characteristic from the corre serviced by interrupt service routines that youOTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determineSee PTS control block directly to the interrupt service routine whenprioritized interrupt transitions from different actual characteristics taken ideal A/D converterquantizing error repeatability errorthe A/D converter Successive approximation register. A component ofsample delay service routine scaled to remove zero-offset error and full-scalecharacteristic of the A/D converter interrupt controller for processing by an interruptprocess quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearityisolation, and VCC rejection errors characteristicPage Index Page INDEX 87C196CB SUPPLEMENT Index-2