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Intel 8XC196NT 87C196CB SUPPLEMENT, 2. Extended Port I/O Direction EPDIR Register, Epdir, Epmode

Models: 8XC196NT 87C196CB

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EP_DIR

87C196CB SUPPLEMENT

EP_DIR	Address:	1FE3H
	Reset State:	FFH

In I/O mode, each bit of the extended port I/O direction (EP_DIR) register controls the direction of the corresponding pin. Clearing a bit configures a pin as a complementary output; setting a bit configures a pin as either an input or an open-drain output. (Open-drain outputs require external pull-ups).

Any pin that is configured for its extended-address function is forced to the complementary output mode except during reset, hold, idle, and powerdown.

7

PIN7	PIN6	PIN5	PIN4

0

PIN3	PIN2	PIN1	PIN0

Bit	Bit		Function
Number	Mnemonic		Function
Number	Mnemonic

7:0	PIN7:0	Extended Address Port Pin x Direction
		This bit configures EPORT.x as a complementary output or an
		input/open-drain output.
		0	= complementary output
		1	= input or an open-drain output

Figure 5-2. Extended Port I/O Direction (EP_DIR) Register

EP_MODE	Address:	1FE1H
	Reset State:	FFH

Each bit of the extended port mode (EP_MODE) register controls whether the corresponding pin functions as a standard I/O port pin or as an extended-address signal. Setting a bit configures a pin as an extended-address signal; clearing a bit configures a pin as a standard I/O port pin.

7

0

PIN7

PIN6

PIN5

PIN4 PIN3

PIN2

PIN1

PIN0

Bit	Bit		Function
Number	Mnemonic		Function
Number	Mnemonic

7:0	PIN7:0	Extended Address Port Pin x Mode
		This bit determines the mode of EPORT.x:
		0	= standard I/O port pin
		1	= extended-address signal

Figure 5-3. Extended Port Mode (EP_MODE) Register

5-2

Image 51

Intel 8XC196NT 87C196CB SUPPLEMENT, 2. Extended Port I/O Direction EPDIR Register, 3. Extended Port Mode EPMODE Register

Contents

87C196CB Supplement to 8XC196NT User’s Manual 87C196CB Supplement to 8XC196NT User’s Manual AugustOrder Number Copyright Intel Corporation, 1998 CHAPTER CONTENTSCHAPTER GUIDE TO THIS MANUALSPECIAL OPERATING MODES SIGNAL DESCRIPTIONS87C196CB SUPPLEMENT CHAPTEREffect of Clock Mode on CLKOUT Frequency FIGURESCONTENTS Internal Clock Phases87C196CB 100-pin QFP Package FIGURES8XC196CB SUPPLEMENT PageTABLES CONTENTSPage Page Guide to This Manual Page CHAPTER GUIDE TO THIS MANUAL 1.1 MANUAL CONTENTS1.2 RELATED DOCUMENTS Appendix A - Signal DescriptionsChapter 9 - Interfacing with External Memory Architectural Overview Page CHAPTER ARCHITECTURAL OVERVIEW 2.1 DEVICE FEATURES2.3 INTERNAL TIMING 2.2 BLOCK DIAGRAMPage 20 MHz 8 MHz12 MHz 16 MHzInput Frequency to Figure 2-4. Effect of Clock Mode on CLKOUT FrequencyARCHITECTURAL OVERVIEW FrequencyPage Memory Partitions Page 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING CHAPTER MEMORY PARTITIONSAddress 87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory MapSIO and SSIO SFRs Timer 1, Timer 2, and EPA SFRsMEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRs Ports 0, 1, 2, and 6 SFRs87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs 1EDCH1ECCH Message MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued128-byte Window 87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs32-byte Window 64-byte WindowLocations MEMORY PARTITIONSTable 3-6. Selecting a Window of the Upper Register File Register RAM87C196CB SUPPLEMENT MEMORY PARTITIONS Table 3-7. Selecting a Window of Upper Register RAM0DE0-0DFFH 87C196CB SUPPLEMENT Table 3-8. Windows MEMORY PARTITIONS Table 3-8. Windows ContinuedUpper Register File 87C196CB SUPPLEMENT Table 3-9. WSR Settings and Direct Addresses for Windowable SFRsMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT 128-byte Windows MEMORY PARTITIONS32-byte Windows 64-byte Windows32-byte Windows Standard and PTS Interrupts Page 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES CHAPTER STANDARD AND PTS INTERRUPTSStandard Vector 87C196CB SUPPLEMENTFigure 4-1. Interrupt Mask 1 INTMASK1 Register Figure 4-2. interrupt Pending 1 INTPEND1 RegisterI/O Ports Page 5.1 PORT 0 AND EPORT CHAPTER I/O PORTSEPDIR Figure 5-3. Extended Port Mode EPMODE Register87C196CB SUPPLEMENT Figure 5-2. Extended Port I/O Direction EPDIR RegisterEPPIN I/O PORTSFigure 5-4. Extended Port Input EPPIN Register Figure 5-5. Extended Port Data Output EPREG RegisterPage Analog-to-digital A/D Converter Page 6.1 ADDITIONAL A/D INPUT CHANNELS CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTERFunction Figure 6-1. A/D Command ADCOMMAND RegisterADCOMMAND 87C196CB SUPPLEMENTFunction ANALOG-TO-DIGITAL A/D CONVERTERFigure 6-2. A/D Result ADRESULT Register - Read Format ADRESULT ReadPage CAN Serial Communications Controller Page 7.1 CAN FUNCTIONAL OVERVIEW CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLERPage Table 7-2. Control and Status Registers 7.2 CAN CONTROLLER SIGNALS AND REGISTERSTable 7-1. CAN Controller Signals CAN SERIAL COMMUNICATIONS CONTROLLER87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued 7.3 CAN CONTROLLER OPERATION7.3.2 Message Objects 7.3.1 Address Map7.3.2.2 Message Acceptance Filtering Contents87C196CB SUPPLEMENT Table 7-4. Message Object Structure 7.3.2.1 Receive and Transmit Priorities7.3.3 Message Frames Table 7-7. Extended Message Frame 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame7.3.4 Error Detection and Management Logic 7.3.5 Bit Timing SymbolDefinition t SYNC CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-5. A Bit Time as Implemented in the CAN Controller Table 7-9. CAN Controller Bit Time SegmentsTable 7-10. Bit Timing Relationships whereTable 7-10 defines the bit timing relationships of the CAN controller 87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations7.4.1 Programming the CAN Control CANCON Register 7.4 CONFIGURING THE CAN CONTROLLERThis bit globally enables and disables interrupts error, status-change, and 87C196CB SUPPLEMENTFigure 7-6. CAN Control CANCON Register Continued Unchanged 7.4.2 Programming the Bit Timing 0 CANBTIME0 RegisterTSEG2 7.4.3 Programming the Bit Timing 1 CANBTIME1 Register87C196CB SUPPLEMENT Figure 7-8. CAN Bit Timing 1 CANBTIME1 RegisterComments 7.4.4 Programming a Message Acceptance FilterBit Time Requirement87C196CB 87C196CB SUPPLEMENTFigure 7-9. CAN Standard Global Mask CANSGMSK Register CANSGMSK87C196CB CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-10. CAN Extended Global Mask CANEGMSK Register CANEGMSK7.5 CONFIGURING MESSAGE OBJECTS 87C196CB SUPPLEMENTFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5.1 Specifying a Message Object’s Configuration 7.5.2 Programming the Message Object Identifier 87C196CB SUPPLEMENTFigure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.3 Programming the Message Object Control Registers 7.5.4 Programming the Message Object DataAccess Type 87C196CB SUPPLEMENT Figure 7-14. CAN Message Object x Control 0 CANMSGxCON0 RegisterProgram the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 Register 87C196CB SUPPLEMENTCAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-16. CAN Message Object Data CANMSGxDATA0-7 RegistersFunction 7.6 ENABLING THE CAN INTERRUPTS 87C196CB 87C196CB SUPPLEMENTFigure 7-17. CAN Control CANCON Register Continued CANCON ContinuedWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS Figure 7-20. CAN Status CANSTAT Register CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register 87C196CB SUPPLEMENTRegister Mnemonic 7.8 FLOW DIAGRAMSA2594-01 Process message contents87C196CB SUPPLEMENT Figure 7-22. Receiving a Message for Message Objects 1-14 - CPU FlowCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-23. Receiving a Message for Message Object 15 - CPU FlowRestart Process same identifer as this 87C196CB SUPPLEMENTFigure 7-24. Receiving a Message - CAN Controller Flow Received frame withFigure 7-25. Transmitting a Message - CPU Flow Power UpUpdate CAN SERIAL COMMUNICATIONS CONTROLLERwith same identifer as 87C196CB SUPPLEMENTFigure 7-26. Transmitting a Message - CAN Controller Flow Received remote frame7.9.3 Bus-off State 7.9.1 Hardware Reset7.9 DESIGN CONSIDERATIONS 7.9.2 Software InitializationThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page CHAPTER SPECIAL OPERATING MODES 8.1 CLOCK CIRCUITRYFigure 8-1. Clock Circuitry Page Interfacing with External Memory Page 9.1 ADDRESS PINS CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY9.2 BUS TIMING MODES T AVDV = 3t 87C196CB SUPPLEMENTFigure 9-1. Modes 0 and 3 Timings T RLDV = 1tINTERFACING WITH EXTERNAL MEMORY Figure 9-2. Chip Configuration 1 CCR1 Registerno direct access † = always enabledFunction Figure 9-2. Chip Configuration 1 CCR1 Register Continued87C196CB SUPPLEMENT CCR1 ContinuedProgramming the Nonvolatile Memory Page 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODE CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING 87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory MapTable 10-3. Auto Programming Memory Map 74HC14 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMINGPROGRAMMING THE NONVOLATILE MEMORY Figure 10-1. Auto Programming Circuit10.4.1 Selecting Bank 0 FF2000-FF7FFFH 10.4.2 Selecting Bank 1 FF8000-FFFFFFHSerial Port Programming Mode Signal Descriptions Page A.1 FUNCTIONAL GROUPINGS OF SIGNALS APPENDIX A SIGNAL DESCRIPTIONSView of component as 87C196CB SupplementFigure A-1. 87C196CB 84-pin PLCC Package xx87C196CBxx87C196CB A.2 SIGNAL DESCRIPTIONSSIGNAL DESCRIPTIONS Figure A-2. 87C196CB 100-pin QFP PackageTable A-3. Signal Descriptions 87C196CB SupplementTable A-2. Description of Columns of Table A-3 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions Continuedread or write. AINC# is sampled after each location is programmed or dumped 87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONS87C196CB Supplement Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued 87C196CB SupplementA-10 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-11 Table A-3. Signal Descriptions Continued 87C196CB SupplementA-12 SIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-13 87C196CB Supplement A.3 DEFAULT CONDITIONSTable A-3. Signal Descriptions Continued Table A-4. Definition of Status SymbolsSIGNAL DESCRIPTIONS Table A-5. 87C196CB Pin Status ContinuedA-15 Page Glossary Page GLOSSARY characteristic transfer function of an A/D convertertwo adjacent code transitions on the A/D converter channel-to-channel matching errorcode width earity errorsSee off-isolation conversion result. Differential nonlinearity is astarting address of an interrupt service routine The characteristic of an ideal A/D converter. An ideallinearity errors. Quantizing error is the only error are to be serviced by interrupt service routines thatSee interrupt service routine See differential nonlinearity and nonlinearitylinearity errors Embedded Microcontrollers databook to determine terminal-based characteristic from the correserviced by interrupt service routines that you OTPROM. Consult the Automotive Products ordirectly to the interrupt service routine when See PTS control blockprioritized interrupt repeatability error transitions from different actual characteristics takenideal A/D converter quantizing errorSuccessive approximation register. A component of the A/D convertersample delay interrupt controller for processing by an interrupt service routinescaled to remove zero-offset error and full-scale characteristic of the A/D convertercharacteristic process quantizing error, zero-offset error, full-scaleerror, differential nonlinearity, and nonlinearity isolation, and VCC rejection errorsPage Index Page INDEX Index-2 87C196CB SUPPLEMENT