Intel 87C196CB, 8XC196NT user manual Table A-3. Signal Descriptions Continued

SIGNAL DESCRIPTIONS

		Table A-3. Signal Descriptions (Continued)
Name	Type			Description
ADV#	O	Address Valid
		This active-low output signal is asserted only during external memory
		accesses. ADV# indicates that valid address information is available on the
		system address/data bus. The signal remains low while a valid bus cycle is in
		progress and is returned high as soon as the bus cycle completes.
		An external latch can use this signal to demultiplex the address from the
		address/data bus. A decoder can also use this signal to generate chip selects
		for external memory.
		ADV# is multiplexed with P5.0, SLPALE, and ALE.
AINC#	I	Auto Increment
		During slave programming, this active-low input enables the auto-increment
		feature. (Auto increment allows reading or writing of sequential OTPROM
		locations, without requiring address transactions across the PBUS for each
		read or write.) AINC# is sampled after each location is programmed or dumped.
		If AINC# is asserted, the address is incremented and the next data word is
		programmed or dumped.
		AINC# is multiplexed with P2.4 and INTOUT#.
ALE	O	Address Latch Enable
		This active-high output signal is asserted only during external memory cycles.
		ALE signals the start of an external bus cycle and indicates that valid address
		information is available on the system address/data bus. ALE differs from ADV#
		in that it does not remain active during the entire bus cycle.
		An external latch can use this signal to demultiplex address from the
		address/data bus.
		ALE is multiplexed with P5.0, SLPALE, and ADV#.
ANGND	GND	Analog Ground
		ANGND must be connected for A/D converter and port 0 operation. ANGND
		and VSS should be nominally at the same potential.
BHE#	O	Byte High Enable†
		During 16-bit bus cycles, this active-low output signal is asserted for word reads
		and writes and high-byte reads and writes to external memory. BHE# indicates
		that valid data is being transferred over the upper half of the system data bus.
		Use BHE#, in conjunction with AD0, to determine which memory byte is being
		transferred over the system bus:
		BHE#	AD0	Byte(s) Accessed
		0	0	both bytes
		0	1	high byte only
		1	0	low byte only
		BHE# is multiplexed with P5.5 and WRH#.
		† The chip configuration register 0 (CCR0) determines whether this pin
		functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
		WRH#.

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