Intel 8XC196NT, 87C196CB where, 10 defines the bit timing relationships of the CAN controller

87C196CB SUPPLEMENT

7.3.5.1Bit Timing Equations

The bit timing equations of the integrated CAN controller are equivalent to those for the 82527 CAN peripheral with the DSC bit in the CPU interface register set (system clock divided by two). The following equations show the timing calculations for the integrated CAN controller and the 82527 CAN peripheral, respectively.

CAN Controller CAN bus frequency =			Fosc
			×-----(---BRP--------------+-----1----)---×-----(--3-----+-----TSEG1---------------------+-----TSEG2----------------------)
	2
			Fosc
82527 CAN bus frequency = (DSC + 1) × (BRP + 1) × (3 + TSEG1 + TSEG2)--------------------------------------------------------------------------------------------------------------------------------
where:
FOSC	= the input clock frequency on the XTAL1 pin, in MHz
BRP	= the value of the BRP bit in bit timing register 0
TSEG1	= the value of the TSEG1 field in bit timing register 0
TSEG2	= the value of the TSEG1 field in bit timing register 1
Table 7-10 defines the bit timing relationships of the CAN controller.
		Table 7-10. Bit Timing Relationships
Timing			Definition
Parameter
tBITTIME		tSYNC_SEG + tTSEG1 + tTSEG2
tXTAL1		input clock period on XTAL1 (50 ns at 20 MHz operation)
tq		2tXTAL1 × (BRP + 1), where BRP is a field in bit timing register 0 (valid values are 0–63)
tSYNC_SEG		1tq
tTSEG1		(TSEG1 + 1) × tq, where TSEG1 is a field in bit timing register 1 (valid values are 2–15)
tTSEG2		(TSEG2 + 1) × tq, where TSEG2 is a field in bit timing register 1 (valid values are 1–7)
tSJW		(SJW + 1) × tq, where SJW is a field in bit timing register 0 (valid values are 0–3)
tPROP		The portion of tTSEG1 that is equivalent to PROP_SEG as defined by the CAN protocol. Twice
		the maximum sum of the physical bus delay, input comparator delay, and output driver delay,
		rounded up to the nearest multiple of tq.

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