A
A/D converter, signals, 6-1 AD_COMMAND register, 6-2 AD_RESULT register, 6-3 Auto programming mode
circuit, 10-3 memory map, 10-2
B
Block diagram
CAN peripheral, 7-2 clock circuitry, 2-2core and peripherals, 2-2
Bus-timing modes, 9-1–9-2comparison, 9-1,9-2
C
CAN serial communications controller, 7-1–7-42 address map, 7-5
bit timing, 7-10–7-12 block diagram, 7-2 bus-off state, 7-41
error detection and management logic, 7-9 message
acceptance filtering, 7-6 frames, 7-7
extended, 7-8 standard, 7-8
identifiers, effect of masking on, 7-7 objects, 7-5–7-6
overview, 7-1–7-2 programming, 7-4–7-31
receive and transmit priorities, 7-6 registers, 7-3–7-4
signals, 7-3 CAN_BTIME0 register, 7-3, 7-15 CAN_BTIME1 register, 7-3, 7-16 CAN_CON register, 7-3, 7-13, 7-29 CAN_EGMSK register, 7-3, 7-19 CAN_INT register, 7-3, 7-32 CAN_MSGxCFG register, 7-3, 7-21
CAN_MSGxCON0 register, 7-3, 7-24, 7-31, 7-34 CAN_MSGxCON1 register, 7-4, 7-26
INDEX
CAN_MSGxDATA0-7 register, 7-28 CAN_MSGxDATAx register, 7-4 CAN_MSGxID register, 7-4 CAN_MSGxID0-3 register, 7-22 CAN_MSK15 register, 7-4, 7-20 CAN_SGMSK register, 7-4, 7-18 CAN_STAT register, 7-4, 7-33 CCR1 register, 9-3
CLKOUT, and internal timing, 2-2–2-4 Clock circuitry, 2-3
Clock phases, internal, 2-4
D
Documents, related, 1-2
E
EP_DIR register, 5-2
EP_MODE register, 5-2
EPORT, 5-1
EP_PIN register, 5-3
EP_REG register, 5-3
F
Formulas
clock period (t), 2-4
PH1 and PH2 frequency, 2-4
state time, 2-4
Frequency (f), 2-4
FXTAL1, 2-4
I
Idle mode, pin status, A-14
Interrupts, 4-1
INT_MASK1 register, 4-2
INT_PEND1 register, 4-2
M
Manual contents, summary, 1-1 Memory mapping
auto programming mode, 10-2 serial port programming mode, 10-3