Intel 87C196CB, 8XC196NT user manual Clock Circuitry

ARCHITECTURAL OVERVIEW

	Disable
	PLL
	(Powerdown)
FXTAL1				Phase	Filter
XTAL1				Comparator
	XTAL1			Phase-
				locked
XTAL2	F
	XTAL1			Oscillator
Disable		Disable Clock Input
	4F			Phase-locked Loop
Oscillator		(Powerdown)
				Clock Multiplier
(Powerdown)
	f	Divide-by-two
		Circuit
PLLEN		f	Disable Clocks
		2	(Powerdown)
				Peripheral Clocks (PH1, PH2)
		Clock		CLKOUT
		Generators
				CPU Clocks (PH1, PH2)
			Disable Clocks
		(Idle, Powerdown)
					A3168-01

Figure 2-2. Clock Circuitry

The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil- ity in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

2-3