Intel 8XC196NT, 87C196CB user manual Can Controller Operation

87C196CB SUPPLEMENT

Table 7-2. Control and Status Registers (Continued)

Register	Register	Description
Mnemonic ††	Address ††
CAN_MSGxCON1	1Ey1H	Message Object x Control 1
		Program this register to indicate that a message is ready to
		transmit or to initiate a transmission. Read this register to
		determine whether the message object contains new data,
		whether a message has been overwritten, whether software is
		updating the message, and whether a transfer is pending.
CAN_MSGxDATA0	1Ey7H	Message Object x Data 0–7
CAN_MSGxDATA1	1Ey8H	The data registers contain data to be transmitted or data received.
CAN_MSGxDATA2	1Ey9H
		Do not use unused data bytes as scratch-pad memory; the CAN
CAN_MSGxDATA3	1EyAH
		controller writes random values to these registers during
CAN_MSGxDATA4	1EyBH
		operation.
CAN_MSGxDATA5	1EyCH
CAN_MSGxDATA6	1EyDH
CAN_MSGxDATA7	1EyEH
CAN_MSGxID0	1Ey2H	Message Object x Identification 0–3
CAN_MSGxID1	1Ey3H	Write the message object’s ID to this register. (This register is the
CAN_MSGxID2	1Ey4H
		same as the arbitration register of the 82527.)
CAN_MSGxID3	1Ey5H
CAN_MSK15	1E0CH, 1E0DH,	Message 15 Mask
	1E0EH, 1E0FH	Program this register to mask (“don’t care”) specific message
		identifier bits for message 15 in addition to those bits masked by a
		global mask. The message 15 mask is ANDed with the standard
		or extended global mask, so any “don’t care” bits defined in a
		global mask are also “don’t care” bits for message 15.
CAN_SGMSK	1E06H, 1E07H	Standard Global Mask
		Program this register to mask (“don’t care”) specific message
		identifier bits for standard message objects.
CAN_STAT	1E01H	Status
		This register reflects the current status of the CAN controller.
INT_MASK1	0013H	Interrupt Mask 1
		The CAN bit in this register enables and disables the CAN
		interrupt request.
INT_PEND1	0012H	Interrupt Pending 1
		The CAN bit in this register, when set, indicates a pending CAN
		interrupt request.

†The CCE bit in CAN_CON must be set to enable write access to the bit timing registers. †† In register names, x = 1–15; in addresses, y = 1–F.

7.3CAN CONTROLLER OPERATION

This section describes the address map, message objects, message frames (which contain mes- sage objects), error detection and management logic, and bit timing for CAN transmissions and receptions.

7-4