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Intel 87C196CB, 8XC196NT user manual Message Frames

Models: 8XC196NT 87C196CB

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7.3.3Message Frames

CAN SERIAL COMMUNICATIONS CONTROLLER

Table 7-5. Effect of Masking on Message Identifiers

Transmit message object ID	1 1 0 0 0 0 0 0 0 0 0

Mask (0 = don’t care; 1 = must match)	0 0 0 0 0 0 0 0 0 1 1

Received remote message object ID	0 0 1 1 1 1 1 1 1 0 0


Resulting message object ID	0 0 1 1 1 1 1 1 1 0 0

7.3.3Message Frames

A message object is contained within a message frame that adds control and error-detectionbits to the content of the message object. The frame for an extended message differs slightly from that for a standard message, but they contain similar information. A data frame contains a message object with data to be transmitted; a remote frame is a request for another node to transmit a data frame, so it contains no data.

Figure 7-3 illustrates standard and extended message frames. Table 7-6 and Table 7-7 describe their contents and summarize the minimum message lengths. Actual message lengths may differ because the CAN controller adds bits during transmission (see “Error Detection and Management Logic” on page 7-9). After each message frame, an intermission field consisting of three recessive

(1) bits separates messages. This intermission may be followed by a bus idle time.

Standard Frame											End of
											Frame
				Arbitration			Control		Data Field	CRC	Ack
				Field			Field		Data Field	Field	F.
				Field			Field			Field	F.
			S	11-bit	R	I				15-bit
			O	11-bit	R	I	r	DLC
			O	Identifier	T	D			0–8 Bytes
			F	Identifier	T	D			0–8 Bytes	CRC
			F		R	E	0			CRC
Extended Frame											End of
											Frame
			Arbitration				Control		Data Field	CRC	Ack
			Field				Field		Data Field	Field	F.
			Field				Field			Field	F.
S	11 bit	S	I	18-bit	R					15-bit
O	11 bit	R	D	18-bit	T	r	r	DLC	0–8 Bytes	15-bit
O	Identifier	R	D	Identifier	T	r	r	DLC		CRC
F	Identifier	R	E	Identifier	R	1	0			CRC
F		R	E		R	1	0
											A2599-01

Figure 7-3. CAN Message Frames

7-7

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Intel 87C196CB, 8XC196NT user manual Message Frames

Contents

87C196CB Supplement to 8XC196NT User’s Manual Order Number 87C196CB Supplement to 8XC196NT User’s ManualAugust Copyright Intel Corporation, 1998 CONTENTS CHAPTERGUIDE TO THIS MANUAL CHAPTERSIGNAL DESCRIPTIONS 87C196CB SUPPLEMENTCHAPTER SPECIAL OPERATING MODESFIGURES CONTENTSInternal Clock Phases Effect of Clock Mode on CLKOUT FrequencyFIGURES 8XC196CB SUPPLEMENTPage 87C196CB 100-pin QFP PackagePage TABLESCONTENTS Page Guide to This Manual Page 1.1 MANUAL CONTENTS CHAPTER GUIDE TO THIS MANUALChapter 9 - Interfacing with External Memory 1.2 RELATED DOCUMENTSAppendix A - Signal Descriptions Architectural Overview Page 2.1 DEVICE FEATURES CHAPTER ARCHITECTURAL OVERVIEW2.2 BLOCK DIAGRAM 2.3 INTERNAL TIMINGPage 8 MHz 12 MHz16 MHz 20 MHzFigure 2-4. Effect of Clock Mode on CLKOUT Frequency ARCHITECTURAL OVERVIEWFrequency Input Frequency toPage Memory Partitions Page CHAPTER MEMORY PARTITIONS 3.1 MEMORY MAP, SPECIAL-FUNCTION REGISTERS, AND WINDOWING87C196CB SUPPLEMENT Table 3-2. 87C196CB Memory Map AddressTimer 1, Timer 2, and EPA SFRs MEMORY PARTITIONS Table 3-3. 87C196CB Peripheral SFRsPorts 0, 1, 2, and 6 SFRs SIO and SSIO SFRs1ECCH 87C196CB SUPPLEMENT Table 3-4. CAN Peripheral SFRs1EDCH MEMORY PARTITIONS Table 3-4. CAN Peripheral SFRs Continued Message87C196CB SUPPLEMENT Table 3-5. Selecting a Window of Peripheral SFRs 32-byte Window64-byte Window 128-byte WindowMEMORY PARTITIONS Table 3-6. Selecting a Window of the Upper Register FileRegister RAM Locations87C196CB SUPPLEMENT 0DE0-0DFFH MEMORY PARTITIONSTable 3-7. Selecting a Window of Upper Register RAM 87C196CB SUPPLEMENT Table 3-8. Windows Upper Register File MEMORY PARTITIONSTable 3-8. Windows Continued Table 3-9. WSR Settings and Direct Addresses for Windowable SFRs 87C196CB SUPPLEMENTMEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 87C196CB SUPPLEMENT MEMORY PARTITIONS 32-byte Windows64-byte Windows 128-byte Windows32-byte Windows Standard and PTS Interrupts Page CHAPTER STANDARD AND PTS INTERRUPTS 4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES87C196CB SUPPLEMENT Figure 4-1. Interrupt Mask 1 INTMASK1 RegisterFigure 4-2. interrupt Pending 1 INTPEND1 Register Standard VectorI/O Ports Page CHAPTER I/O PORTS 5.1 PORT 0 AND EPORTFigure 5-3. Extended Port Mode EPMODE Register 87C196CB SUPPLEMENTFigure 5-2. Extended Port I/O Direction EPDIR Register EPDIRI/O PORTS Figure 5-4. Extended Port Input EPPIN RegisterFigure 5-5. Extended Port Data Output EPREG Register EPPINPage Analog-to-digital A/D Converter Page CHAPTER 6 ANALOG-TO-DIGITAL A/D CONVERTER 6.1 ADDITIONAL A/D INPUT CHANNELSFigure 6-1. A/D Command ADCOMMAND Register ADCOMMAND87C196CB SUPPLEMENT FunctionANALOG-TO-DIGITAL A/D CONVERTER Figure 6-2. A/D Result ADRESULT Register - Read FormatADRESULT Read FunctionPage CAN Serial Communications Controller Page CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7.1 CAN FUNCTIONAL OVERVIEWPage 7.2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7-1. CAN Controller SignalsCAN SERIAL COMMUNICATIONS CONTROLLER Table 7-2. Control and Status Registers7.3 CAN CONTROLLER OPERATION 87C196CB SUPPLEMENT Table 7-2. Control and Status Registers Continued7.3.1 Address Map 7.3.2 Message ObjectsContents 87C196CB SUPPLEMENT Table 7-4. Message Object Structure7.3.2.1 Receive and Transmit Priorities 7.3.2.2 Message Acceptance Filtering7.3.3 Message Frames 87C196CB SUPPLEMENT Table 7-6. Standard Message Frame Table 7-7. Extended Message Frame7.3.4 Error Detection and Management Logic Definition 7.3.5 Bit TimingSymbol CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-5. A Bit Time as Implemented in the CAN ControllerTable 7-9. CAN Controller Bit Time Segments t SYNCwhere Table 7-10 defines the bit timing relationships of the CAN controller87C196CB SUPPLEMENT 7.3.5.1 Bit Timing Equations Table 7-10. Bit Timing Relationships7.4 CONFIGURING THE CAN CONTROLLER 7.4.1 Programming the CAN Control CANCON RegisterFigure 7-6. CAN Control CANCON Register Continued This bit globally enables and disables interrupts error, status-change, and87C196CB SUPPLEMENT 7.4.2 Programming the Bit Timing 0 CANBTIME0 Register Unchanged7.4.3 Programming the Bit Timing 1 CANBTIME1 Register 87C196CB SUPPLEMENTFigure 7-8. CAN Bit Timing 1 CANBTIME1 Register TSEG27.4.4 Programming a Message Acceptance Filter Bit TimeRequirement Comments87C196CB SUPPLEMENT Figure 7-9. CAN Standard Global Mask CANSGMSK RegisterCANSGMSK 87C196CBCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-10. CAN Extended Global Mask CANEGMSK RegisterCANEGMSK 87C196CBFigure 7-11. CAN Message 15 Mask CANMSK15 Register 7.5 CONFIGURING MESSAGE OBJECTS87C196CB SUPPLEMENT 7.5.1 Specifying a Message Object’s Configuration Figure 7-13. CAN Message Object x Identifier CANMSGxID0-3 Register 7.5.2 Programming the Message Object Identifier87C196CB SUPPLEMENT Access Type 7.5.3 Programming the Message Object Control Registers7.5.4 Programming the Message Object Data Program the CAN message object x control 0 CANMSGxCON0 register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt. The least-significant bit-pair indicates whether an interrupt is pending 87C196CB SUPPLEMENTFigure 7-14. CAN Message Object x Control 0 CANMSGxCON0 Register CAN SERIAL COMMUNICATIONS CONTROLLER 87C196CB SUPPLEMENT Figure 7-15. CAN Message Object x Control 1 CANMSGxCON1 RegisterCAN SERIAL COMMUNICATIONS CONTROLLER Function 87C196CB SUPPLEMENTFigure 7-16. CAN Message Object Data CANMSGxDATA0-7 Registers 7.6 ENABLING THE CAN INTERRUPTS 87C196CB SUPPLEMENT Figure 7-17. CAN Control CANCON Register ContinuedCANCON Continued 87C196CBWhen the SIE bit in the CAN control register is set, the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message, even if no message ob- ject accepts it. If you set both the SIE bit Figure 7-17 and an individual message object’s RXIE bit Figure 7-18, the CAN controller generates two interrupt requests each time a message object receives a message. The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems. However, you should disable this interrupt during normal operation in most applications. If the status change interrupt is enabled, each status change generates an interrupt request, placing an unnecessary burden on the CPU. To prevent re- dundant interrupt requests, enable the error interrupt sources with the EIE bit and enable the re- ceive and transmit interrupts in the individual message objects 7.7 DETERMINING THE CAN CONTROLLER’S INTERRUPT STATUS CAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-20. CAN Status CANSTAT Register87C196CB SUPPLEMENT Figure 7-21. CAN Message Object x Control 0 CANMSGxCON0 Register7.8 FLOW DIAGRAMS Register MnemonicProcess message contents 87C196CB SUPPLEMENTFigure 7-22. Receiving a Message for Message Objects 1-14 - CPU Flow A2594-01Restart Process CAN SERIAL COMMUNICATIONS CONTROLLERFigure 7-23. Receiving a Message for Message Object 15 - CPU Flow 87C196CB SUPPLEMENT Figure 7-24. Receiving a Message - CAN Controller FlowReceived frame with same identifer as thisPower Up UpdateCAN SERIAL COMMUNICATIONS CONTROLLER Figure 7-25. Transmitting a Message - CPU Flow87C196CB SUPPLEMENT Figure 7-26. Transmitting a Message - CAN Controller FlowReceived remote frame with same identifer as7.9.1 Hardware Reset 7.9 DESIGN CONSIDERATIONS7.9.2 Software Initialization 7.9.3 Bus-off StateThe CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occurrences of 11 consecutive recessive bits before participating in bus activities. During this sequence, the CAN controller writes a bit 0 error code to the LEC20 bits of the status register each time it receives a recessive bit. Software can check the status register to determine whether the CAN bus is stuck in a dominant state. Once the CAN controller is resynchronized with the CAN bus, it clears the BUSOFF bit and starts transferring messages again Special Operating Modes Page Figure 8-1. Clock Circuitry CHAPTER SPECIAL OPERATING MODES8.1 CLOCK CIRCUITRY Page Interfacing with External Memory Page 9.2 BUS TIMING MODES 9.1 ADDRESS PINSCHAPTER 9 INTERFACING WITH EXTERNAL MEMORY 87C196CB SUPPLEMENT Figure 9-1. Modes 0 and 3 TimingsT RLDV = 1t T AVDV = 3tFigure 9-2. Chip Configuration 1 CCR1 Register no direct access †= always enabled INTERFACING WITH EXTERNAL MEMORYFigure 9-2. Chip Configuration 1 CCR1 Register Continued 87C196CB SUPPLEMENTCCR1 Continued FunctionProgramming the Nonvolatile Memory Page 10.1 SIGNATURE WORD AND PROGRAMMING VOLTAGES 10.2 MEMORY MAP FOR SLAVE PROGRAMMING MODECHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY Table 10-3. Auto Programming Memory Map 10.3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING87C196CB SUPPLEMENT Table 10-2. Slave Programming Mode Memory Map 10.4 MEMORY MAP FOR SERIAL PORT PROGRAMMING PROGRAMMING THE NONVOLATILE MEMORYFigure 10-1. Auto Programming Circuit 74HC14Serial Port Programming Mode 10.4.1 Selecting Bank 0 FF2000-FF7FFFH10.4.2 Selecting Bank 1 FF8000-FFFFFFH Signal Descriptions Page APPENDIX A SIGNAL DESCRIPTIONS A.1 FUNCTIONAL GROUPINGS OF SIGNALS87C196CB Supplement Figure A-1. 87C196CB 84-pin PLCC Packagexx87C196CB View of component asA.2 SIGNAL DESCRIPTIONS SIGNAL DESCRIPTIONSFigure A-2. 87C196CB 100-pin QFP Package xx87C196CBTable A-2. Description of Columns of Table A-3 Table A-3. Signal Descriptions87C196CB Supplement read or write. AINC# is sampled after each location is programmed or dumped SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued Table A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedTable A-3. Signal Descriptions Continued 87C196CB SupplementSIGNAL DESCRIPTIONS Table A-3. Signal Descriptions ContinuedA-10 Table A-3. Signal Descriptions Continued87C196CB Supplement A-11 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued A-12 Table A-3. Signal Descriptions Continued87C196CB Supplement A-13 SIGNAL DESCRIPTIONSTable A-3. Signal Descriptions Continued A.3 DEFAULT CONDITIONS Table A-3. Signal Descriptions ContinuedTable A-4. Definition of Status Symbols 87C196CB SupplementA-15 SIGNAL DESCRIPTIONSTable A-5. 87C196CB Pin Status Continued Page Glossary Page GLOSSARY transfer function of an A/D converter two adjacent code transitions on the A/D converterchannel-to-channel matching error characteristicearity errors See off-isolationconversion result. Differential nonlinearity is a code widthThe characteristic of an ideal A/D converter. An ideal linearity errors. Quantizing error is the only errorare to be serviced by interrupt service routines that starting address of an interrupt service routinelinearity errors See interrupt service routineSee differential nonlinearity and nonlinearity terminal-based characteristic from the corre serviced by interrupt service routines that youOTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determineprioritized interrupt directly to the interrupt service routine whenSee PTS control block transitions from different actual characteristics taken ideal A/D converterquantizing error repeatability errorsample delay Successive approximation register. A component ofthe A/D converter service routine scaled to remove zero-offset error and full-scalecharacteristic of the A/D converter interrupt controller for processing by an interruptprocess quantizing error, zero-offset error, full-scale error, differential nonlinearity, and nonlinearityisolation, and VCC rejection errors characteristicPage Index Page INDEX 87C196CB SUPPLEMENT Index-2