
•Traditional AGP style traffic (asynchronous
•Peer segment destination posted write traffic (no
•
•
•
•PCI Express* reference clock is
•Power Management Event (PME) functions.
•Dynamic width capability.
•Message Signaled Interrupt (MSI and
•Polarity inversion
Note: The processor does not support PCI Express*
2.2.2PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-
Gen 3 PCI Express* uses a 128b/130b encoding that is about 23% more efficient than the 8b/10b encoding used in Gen 1 and Gen 2.
The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. See the PCI Express Base Specification 3.0 for details of PCI Express* architecture.
2.2.3PCI Express* Configuration Mechanism
The PCI Express* (external graphics) link is mapped through a
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 23 |