Power Management—Processor

Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on an interrupt, even if interrupts are masked by EFLAGS.IF.

4.2.4Core C-State Rules

The following are general rules for all core C-states, unless specified otherwise:

•A core C-state is determined by the lowest numerical thread state (such as Thread 0 requests C1E state while Thread 1 requests C3 state, resulting in a core C1E state). See the G, S, and C Interface State Combinations table.

•A core transitions to C0 state when:

—An interrupt occurs

—There is an access to the monitored address if the state was entered using an MWAIT/Timed MWAIT instruction

—The deadline corresponding to the Timed MWAIT instruction expires

•An interrupt directed toward a single thread wakes only that thread.

•If any thread in a core is in active (in C0 state), the core's C-state will resolve to C0 state.

•Any interrupt coming into the processor package may wake any core.

•A system reset re-initializes all processor cores.

Core C0 State

The normal operating state of a core where code is being executed.

Core C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E state, see Package C-Stateson page 54.

Core C3 State

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the core’s caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

 

Intel® Xeon® Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

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