Processor—Interfaces

2.7Intel® Flexible Display Interface (Intel® FDI)

The Intel Flexible Display Interface (Intel FDI) passes display data from the processor (source) to the PCH (sink) for display through a display interface on the PCH.

Intel FDI supports 2 lanes at 2.7 GT/s fixed frequency. This can be configured to 1 or 2 lanes depending on the bandwidth requirements.

Intel FDI supports 8 bits per color only.

Side band sync pin (FDI_CSYNC).

Side band interrupt pin (DISP_INT). This carries combined interrupt for HPDs of all the ports, AUX and I2C completion events, and so on.

Intel FDI is not encrypted as it drives only VGA and content protection is not supported on VGA.

2.8Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and external components like Super I/O (SIO) and Embedded Controllers (EC) to provide processor temperature, Turbo, TDP, and memory throttling control mechanisms and many other services. PECI is used for platform thermal management and real time control and configuration of processor features and performance.

2.8.1PECI Bus Architecture

The PECI architecture based on wired OR bus that the clients (as processor PECI) can pull up high (with strong drive).

The idle state on the bus is near zero.

The following figure demonstrates PECI design and connectivity. While the host/ originator can be third party PECI host, and one of the PECI client is a processor PECI device.

Intel® Xeon® Processor E3-1200 v3 Product Family

 

Datasheet – Volume 1 of 2

June 2013

36

Order No.: 328907-001