Thermal Management—Processor

Figure 17. Digital Thermal Sensor (DTS) Thermal Profile Definition

Table 19.

Thermal Margin Slope

 

 

 

 

 

 

 

 

 

 

 

 

PCG

Die

TDP (W)

TCC Activation

Temperature

Thermal

 

 

Configuration

 

Temperature (°C)

Control Offset

Margin

 

 

(Native)

 

MSR 1A2h 23:16

MSR 1A2h 15:8

Slope

 

 

Core + GT

 

 

 

(°C / W)

 

 

 

 

 

 

 

 

2013D

4+2 (4+2)

84

100

20

0.654

 

 

 

 

 

 

 

4+0 (4+2)

82

100

20

0.671

 

 

 

 

 

 

 

 

 

 

 

4+2 (4+2)

65

92

6

0.722

 

 

 

 

 

 

 

 

2013C

2+2 (2+2)

54

100

20

1.031

 

 

 

 

 

 

 

 

 

2+1 (2+2)

53

100

20

1.051

 

 

 

 

 

 

 

 

2013B

4+2 (4+2)

45

85

6

0.806

 

 

 

 

 

 

 

 

 

4+2 (4+2)

35

75

6

0.806

 

 

 

 

 

 

 

 

2013A

2+2 (4+2)

35

85

6

1.016

 

 

 

 

 

 

 

2+2 (2+2)

35

85

6

1.021

 

 

 

 

 

 

 

 

 

 

 

2+1 (2+2)

35

90

6

1.141

 

 

 

 

 

 

 

5.4Intel® Xeon® Processor E3-1200 v3 Product Family Thermal Specifications

This section provides thermal specifications (Thermal Profile) and design guidelines for enabled thermal solutions to cool the processor.

 

Intel® Xeon® Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

67