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| Parameter | Min | Max | Units | Notes1 |
| VIH |
| Input High Voltage (other GTL) | VCCIO_TERM * 0.72 | — | V | 2, 4 |
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| RON |
| Buffer on Resistance (CFG/BPM) | 16 | 24 | Ω | — |
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| RON |
| Buffer on Resistance (other GTL) | 12 | 28 | Ω | — |
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| ILI |
| Input Leakage Current | — | ±150 | μA | 3 |
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| Notes: 1. | Unless otherwise noted, all specifications in this table apply to all processor frequencies. |
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| 2. | The VCCIO_OUT referred to in these specifications refers to instantaneous VCCIO_OUT. |
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| 3. | For VIN between 0 V and VCCIO_TERM. Measured when the driver is |
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| 4. | VIH and VOH may experience excursions above VCCIO_TERM. However, input signal drivers must | |||||
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Table 48. | PCI Express* DC Specifications |
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| Symbol |
| Parameter | Min |
| Typ | Max | Units |
| Notes1 |
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| DC Differential Tx Impedance (Gen 1 | 80 |
| — | 120 | Ω |
| 1, 6 | |
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| DC Differential Tx Impedance (Gen 2 and | — |
| — | 120 | Ω |
| 1, 6 | |
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| Gen 3) |
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| DC Common Mode Rx Impedance | 40 |
| — | 60 | Ω |
| 1, 4, 5 | |
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| DC Differential Rx Impedance (Gen1 | 80 |
| — | 120 | Ω |
| 1 | |
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| PEG_RCOMP | Comp Resistance | 24.75 |
| 25 | 25.25 | Ω |
| 2, 3 | |
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| Notes: 1. | See the PCI Express Base Specification for more details. |
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| 2. | PEG_RCOMP should be connected to VCOMP_OUT through a 25 Ω ±1% resistor. |
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| 3. | Intel allows using 24.9 Ω ±1% resistors. |
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| 4. | DC impedance limits are needed to ensure Receiver detect. |
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| 5. | The Rx DC Common Mode Impedance must be present when the Receiver terminations are first | ||||||||
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| enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can | ||||||||
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| start immediately and the 15 Rx Common Mode Impedance (constrained by | ||||||||
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| ±20%) must be within the specified range by the time Detect is entered. |
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| 6. | Low impedance defined during signaling. Parameter is captured for 5.0 GHz by |
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7.8.1PECI DC Characteristics
The PECI interface operates at a nominal voltage set by VCCIO_TERM. The set of DC electrical specifications shown in the following table is used with devices normally
operating from a VCCIO_TERM interface supply.
VCCIO_TERM nominal levels will vary between processor families. All PECI devices will operate at the VCCIO_TERM level determined by the processor installed in the system.
Table 49. | PECI DC Electrical Limits |
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| Symbol | Definition and Conditions | Min | Max | Units |
| Notes1 |
| Rup | Internal pull up resistance | 15 | 45 | Ω |
| 3 |
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| Vin | Input Voltage Range | VCCIO_TERM + | V |
| — | |
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| 0.15 |
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| Vhysteresis | Hysteresis | 0.1 * | N/A | V |
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| VCCIO_TERM |
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| continued... | |
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 99 |