
Signal
Signal Name | Description | Direction / Buffer | |
|
| Type | |
|
|
| |
| Test Data Out: This signal transfers serial test data out | O | |
TDO | of the processor. This signal provides the serial output | ||
Open Drain | |||
| needed for JTAG specification support. | ||
|
| ||
|
|
| |
TMS | Test Mode Select: This is a JTAG specification | I | |
supported signal used by debug tools. | GTL | ||
| |||
|
|
| |
| Test Reset: This signal resets the Test Access Port | I | |
TRST# | (TAP) logic. This signal must be driven low during power | ||
GTL | |||
| on Reset. | ||
|
| ||
|
|
|
6.9Error and Thermal Protection Signals
Table 32. | Error and Thermal Protection Signals |
| |
|
|
|
|
| Signal Name | Description | Direction / Buffer |
|
|
| Type |
|
|
|
|
|
| Catastrophic Error: This signal indicates that the system has |
|
|
| experienced a catastrophic error and cannot continue to |
|
|
| operate. The processor will set this for | O |
| CATERR# | machine check errors or other unrecoverable internal errors. | |
| GTL | ||
|
| CATERR# is used for signaling the following types of errors: | |
|
|
| |
|
| Legacy MCERRs, CATERR# is asserted for 16 BCLKs. Legacy |
|
|
| IERRs, CATERR# remains asserted until warm or cold reset. |
|
|
|
|
|
|
| Platform Environment Control Interface: A serial | I/O |
| PECI | sideband interface to the processor, it is used primarily for | Asynchronous |
|
| thermal, power, and error management. |
|
|
|
|
|
|
| Processor Hot: PROCHOT# goes active when the processor | GTL Input |
|
| temperature monitoring sensor(s) detects that the processor | |
| PROCHOT# | has reached its maximum safe operating temperature. This |
|
| indicates that the processor Thermal Control Circuit (TCC) has |
| |
|
|
| |
|
| been activated, if enabled. This signal can also be driven to |
|
|
| the processor to activate the TCC. |
|
|
|
|
|
|
| Thermal Trip: The processor protects itself from catastrophic | O |
|
| overheating by use of an internal thermal sensor. This sensor | Asynchronous OD |
| THERMTRIP# | is set well above the normal operating temperature to ensure | Asynchronous CMOS |
| that there are no false trips. The processor will stop all |
| |
|
| execution when the junction temperature exceeds |
|
|
| approximately 130 °C. This is signaled to the system by the |
|
|
| THERMTRIP# pin. |
|
|
|
|
|
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 83 |