Table 7. | Valid Three Display Configurations through the Processor |
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| Display 1 |
| Display 2 | Display 3 | Maximum | Maximum | Maximum |
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| Resolution Display | Resolution | Resolution Display |
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| 1 | Display 2 | 3 |
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| HDMI |
| HDMI | DP | 4096x2304 @ 24 Hz | 3840x2160 @ 60 Hz | |
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| 2560x1600 @ 60 Hz | |||||
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| DVI |
| DVI | DP | 1920x1200 @ 60 Hz | 3840x2160 @ 60 Hz | |
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| DP |
| DP | DP |
| 3840x2160 @ 60 Hz |
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| VGA |
| DP | HDMI | 1920x1200 @ 60 Hz | 3840x2160 @ | 4096x2304 @ 24 Hz |
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| 60 Hz | 2560x1600 @ 60 Hz | ||||
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| eDP |
| DP | HDMI | 3840x2160 @ 60 Hz | 3840x2160 @ | 4096x2304 @ 24 Hz |
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| 60 Hz | 2560x1600 @ 60 Hz | ||||
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| eDP |
| DP | DP | 3840x2160 @ 60 Hz | 3840x2160 @ 60 Hz | |
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| eDP |
| HDMI | HDMI | 3840x2160 @ 60 Hz | 4096x2304 @ 24 Hz | |
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| 2560x1600 @ 60 Hz | |||||
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| Notes: 1. Requires support of 2 channel DDR3/DDR3L 1600 MT/s configuration for driving 3 simultaneous | ||||||
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| 3840x2160 @ 60 Hz display resolutions |
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| 2. DP and eDP resolutions in the above table are supported for 4 lanes with link data rate HBR2. | ||||||
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The following table shows the DP/eDP resolutions supported for 1, 2, or 4 lanes depending on link data rate of RBR, HBR, and HBR2.
Table 8. DisplayPort and Embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link Data Rate of RBR, HBR, and HBR2
Link Data Rate |
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| 1 | 2 | 4 |
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RBR | 1064x600 | 1400x1050 | 2240x1400 |
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HBR | 1280x960 | 1920x1200 | 2880x1800 |
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HBR2 | 1920x1200 | 2880x1800 | 3840x2160 |
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Any 3 displays can be supported simultaneously using the following rules:
•Maximum of 2 HDMIs
•Maximum of 2 DVIs
•Maximum of 1 HDMI and 1 DVI
•Any 3 DisplayPort
•One VGA
•One eDP
HDCP is the technology for protecting
The HDCP 1.4 keys are integrated into the processor and customers are not required to physically configure or handle the keys.
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 35 |