Intel BX80646E31230V3, BX80646E31240V3 6.4PCI Express*-BasedInterface Signals, 6.5Display Interface Signals

Signal Description—Processor

Signal Name	Description	Direction /
		Buffer Type
SM_DRAMRST#	DRAM Reset: Reset signal from processor to DRAM devices. One	O
	signal common to all channels.	CMOS
TESTLO_x	TESTLO should be individually connected to VSS through a
	resistor.
Note: 1. PCIe bifurcation support varies with the processor and PCH SKUs used.

6.4PCI Express*-Based Interface Signals

Table 27.	PCI Express* Graphics Interface Signals
	Signal Name	Description	Direction / Buffer Type
	PEG_RCOMP	PCI Express Resistance Compensation	I
			A
	PEG_RXP[15:0]	PCI Express Receive Differential Pair	I
	PEG_RXN[15:0]		PCI Express
	PEG_TXP[15:0]	PCI Express Transmit Differential Pair	O
	PEG_TXN[15:0]		PCI Express

6.5Display Interface Signals

Table 28.	Display Interface Signals
	Signal Name	Description	Direction / Buffer
			Type
	FDI_TXP[1:0]	Intel Flexible Display Interface Transmit Differential Pair	O
	FDI_TXN[1:0]		FDI
	DDIB_TXP[3:0]	Digital Display Interface Transmit Differential Pair	O
	DDIB_TXN[3:0]		FDI
	DDIC_TXP[3:0]	Digital Display Interface Transmit Differential Pair	O
	DDIC_TXN[3:0]		FDI
	DDID_TXP[3:0]	Digital Display Interface Transmit Differential Pair	O
	DDID_TXN[3:0]		FDI
	FDI_CSYNC	Intel Flexible Display Interface Sync	I
			CMOS
	DISP_INT	Intel Flexible Display Interface Hot-Plug Interrupt	I
			Asynchronous
			CMOS

	Intel® Xeon® Processor E3-1200 v3 Product Family
June 2013	Datasheet – Volume 1 of 2
Order No.: 328907-001	81