Electrical Specifications—Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

Typ

Max

Units

Notes1

 

 

 

 

DDR3/DDR3L Control

 

25

31

Ω

5, 11,

 

RON_DN(CTL)

 

Buffer pull-down

19

 

 

 

13

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR3/DDR3L Reset

40

80

130

Ω

 

RON_UP(RST)

 

Buffer pull-up

 

 

 

 

 

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR3/DDR3L Reset

 

 

 

 

 

 

RON_DN(RST)

 

Buffer pull-up

40

80

130

Ω

 

 

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Leakage Current

 

 

 

 

 

 

 

 

 

(DQ, CK)

 

 

 

 

 

 

ILI

 

 

0 V

0.7

mA

 

 

 

 

0.2*VDDQ

 

 

 

 

 

 

 

 

 

0.8*VDDQ

 

 

 

 

 

 

 

 

 

Input Leakage Current

 

 

 

 

 

 

 

 

 

(CMD, CTL)

 

 

 

 

 

 

ILI

 

 

0V

1.0

mA

 

 

 

 

0.2*VDDQ

 

 

 

 

 

 

 

 

 

0.8*VDDQ

 

 

 

 

 

 

SM_RCOMP0

 

Command COMP

99

100

101

Ω

8

 

 

Resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SM_RCOMP1

 

Data COMP Resistance

74.25

75

75.75

Ω

8

 

 

 

 

 

 

 

 

 

 

SM_RCOMP2

 

ODT COMP Resistance

99

100

101

Ω

8

 

 

 

 

 

 

 

 

 

 

Notes: 1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

 

 

2.

VIL

is defined as the maximum voltage level at a receiving agent that will be interpreted as a

 

 

logical low value.

 

 

 

 

 

 

3.

VIH

is defined as the minimum voltage level at a receiving agent that will be interpreted as a

 

 

logical high value.

 

 

 

 

 

 

4.

VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply

 

 

with the signal quality specifications.

 

 

 

 

 

 

5.

This is the pull up/down driver resistance.

 

 

 

 

 

6.

RTERM is the termination on the DIMM and in not controlled by the processor.

 

 

 

7.

The minimum and maximum values for these signals are programmable by BIOS to one of the

 

 

two sets.

 

 

 

 

 

 

8.

SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx

 

 

resistors are to VSS. DDR3/DDR3L values are pre-silicon estimations and are subject to change.

 

9.

SM_DRAMPWROK rise and fall time must be < 50 ns measured between VDDQ *0.15 and VDDQ

 

 

*0.47.

 

 

 

 

 

 

 

10.SM_VREF is defined as VDDQ/2

 

 

 

 

 

 

11.Maximum-minimum range is correct but center point is subject to change during MRC boot

 

 

training.

 

 

 

 

 

 

12.Processor may be damaged if VIH exceeds the maximum voltage for extended periods.

 

 

13.The MRC during boot training might optimize RON outside the range specified.

 

 

Table 44.

Digital Display Interface Group DC Specifications

 

 

 

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

VIL

HPD Input Low Voltage

0.8

V

 

 

 

 

 

 

 

 

VIH

HPD Input High Voltage

2.25

3.6

V

 

 

 

 

 

 

 

 

Vaux(Tx)

Aux peak-to-peak voltage at transmitting

0.39

1.38

V

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vaux(Rx)

Aux peak-to-peak voltage at receiving

0.32

1.36

V

 

device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® Xeon® Processor E3-1200 v3 Product Family

June 2013

 

 

 

 

Datasheet – Volume 1 of 2

Order No.: 328907-001

 

 

 

 

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