Intel BX80646E31230V3, BX80646E31240V3 24

									Processor—Interfaces
Figure 3.	PCI Express* Related Register Structures in the Processor



					PCI-PCI
					Bridge				PCI
					Bridge				PCI
		PCI	PEG0		representing				Compatible
		Express*	PEG0		root PCI				Host Bridge
		Express*			root PCI				Host Bridge
		Device			Express ports				Device
					(Device 1 and				(Device 0)
					Device 6)



						DMI

PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification. PCI Express* configuration space is divided into a PCI-compatible region (that consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (that consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section.

The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express* Enhanced configuration mechanisms and transaction rules.

PCI Express* Lanes Connection

The following figure demonstrates the PCIe* lane mapping.

Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2	June 2013
24	Order No.: 328907-001

Contents

Datasheet – Volume 1 of Page Contents Page Figures Tables Page Revision History 1.0Introduction 1.1Supported Technologies 1.2Interfaces 1.3Power Management Support 1.4Thermal Management Support 1.5Package Support 1.6Terminology Page Page 1.7Related Documents Page 2.0Interfaces 2.1System Memory Interface 2.1.1System Memory Technology Supported 2.1.2System Memory Timing Support 2.1.3System Memory Organization Modes Page 2.1.3.1System Memory Frequency 2.1.3.2Intel® Fast Memory Access (Intel® FMA) Technology Enhancements 2.1.3.3Data Scrambling 2.2PCI Express* Interface 2.2.1PCI Express* Support 2.2.2PCI Express* Architecture 2.2.3PCI Express* Configuration Mechanism Page 2.3Direct Media Interface (DMI) Page 2.4Processor Graphics 2.5Processor Graphics Controller (GT) 2.5.13D and Video Engines for Graphics Processing Page 2.5.2Multi Graphics Controllers Multi-MonitorSupport 2.6Digital Display Interface (DDI) Page Source Device Sink Device HDMI Source HDMI Sink Page Page 2.7Intel® Flexible Display Interface (Intel® FDI) 2.8Platform Environmental Control Interface (PECI) 2.8.1PECI Bus Architecture Page 3.0Technologies 3.1Intel® Virtualization Technology (Intel® VT) Page Page Page 3.2Intel® Trusted Execution Technology (Intel® TXT) 3.3Intel® Hyper-ThreadingTechnology (Intel® HT Technology) 3.4Intel® Turbo Boost Technology 3.5Intel® Advanced Vector Extensions 2.0 (Intel® AVX2) 3.6Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) 3.7Intel® Transactional Synchronization Extensions (Intel® TSX) 3.8Intel® 64 Architecture x2APIC 3.9Power Aware Interrupt Routing (PAIR) 3.10Execute Disable Bit 3.11Supervisor Mode Execution Protection (SMEP) 4.0Power Management 4.1Advanced Configuration and Power Interface (ACPI) States Supported 4.2Processor Core Power Management 4.2.1Enhanced Intel® SpeedStep® Technology Key Features 4.2.2Low-PowerIdle States 4.2.3Requesting Low-PowerIdle States 4.2.4Core C-StateRules 4.2.5Package C-States Page Page Page 4.3Integrated Memory Controller (IMC) Power Management 4.3.1Disabling Unused System Memory Outputs 4.3.2DRAM Power Management and Initialization 4.3.2.1Initialization Role of CKE 4.3.3DRAM Running Average Power Limitation (RAPL) 4.3.4DDR Electrical Power Gating (EPG) 4.4PCI Express* Power Management 4.5Direct Media Interface (DMI) Power Management 4.6Graphics Power Management 4.6.1Intel® Rapid Memory Power Management (Intel® RMPM) 4.6.2Graphics Render C-State Page 5.0Thermal Management 5.1Thermal Metrology 5.2Fan Speed Control Scheme with Digital Thermal Sensor (DTS) Page 5.3Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 5.4Intel® Xeon® Processor E3-1200v3 Product Family Thermal Specifications Page 5.5Processor Temperature 5.6Adaptive Thermal Monitor Page Page 5.7THERMTRIP# Signal 5.8Digital Thermal Sensor 5.8.1Digital Thermal Sensor Accuracy (Taccuracy) 5.9Intel® Turbo Boost Technology Thermal Considerations 5.9.1Intel® Turbo Boost Technology Power Control and Reporting 5.9.2Package Power Control 5.9.3Turbo Time Parameter Page 6.0Signal Description 6.1System Memory Interface Signals Page 6.2Memory Reference and Compensation 6.3Reset and Miscellaneous Signals 6.4PCI Express*-BasedInterface Signals 6.5Display Interface Signals 6.6Direct Media Interface (DMI) 6.7Phase Locked Loop (PLL) Signals 6.8Testability Signals 6.9Error and Thermal Protection Signals 6.10Power Sequencing 6.11Processor Power Signals 6.12Sense Pins 6.13Ground and Non-Criticalto Function (NCTF) Signals 6.14Processor Internal Pull-Up / Pull-DownTerminations 7.0Electrical Specifications 7.1Integrated Voltage Regulator 7.2Power and Ground Lands 7.3VCC Voltage Identification (VID) Page Page Page Page 7.4Reserved or Unused Signals 7.5Signal Groups Page 7.6Test Access Port (TAP) Connection 7.7DC Specifications 7.8Voltage and Current Specifications Page Page Page Page 7.8.1PECI DC Characteristics 7.8.2Input Device Hysteresis 8.0Package Mechanical Specifications 8.1Processor Component Keep-OutZone 8.2Package Loading Specifications 8.3Package Handling Guidelines 8.4Package Insertion Specifications 8.5Processor Mass Specification 8.6Processor Materials 8.7 Processor Markings 8.8Processor Land Coordinates 8.9Processor Storage Specifications Page 9.0Processor Ball and Signal Information