| | | | | | | | | Processor—Interfaces |
Figure 3. | PCI Express* Related Register Structures in the Processor |
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| | | | | PCI-PCI | | | | | | |
| | | | | Bridge | | | | PCI | | |
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| | PCI | PEG0 | | representing | | | | Compatible | | |
| | Express* | | root PCI | | | | Host Bridge | | |
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| | Device | | | Express ports | | | | Device | | |
| | | | | (Device 1 and | | | | (Device 0) | | |
| | | | | Device 6) | | | | | | |
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| | | | | | DMI |
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PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification. PCI Express* configuration space is divided into a PCI-compatible region (that consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (that consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section.
The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express* Enhanced configuration mechanisms and transaction rules.
PCI Express* Lanes Connection
The following figure demonstrates the PCIe* lane mapping.
Intel® Xeon® Processor E3-1200 v3 Product Family | |
Datasheet – Volume 1 of 2 | June 2013 |
24 | Order No.: 328907-001 |