Figure 4. PCI Express* Typical Operation 16 Lanes Mapping
1 X 4 Controller
0
1
2
3
1 X 8 Controller
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7
1 X 16 Controller
0
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Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
Lane 12
Lane 13
Lane 14
Lane 15
0
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2.3Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. Next generation DMI2 is supported.
Note: Only DMI x4 configuration is supported.
•DMI 2.0 support.
•Compliant to Direct Media Interface Second Generation (DMI2).
•Four lanes in each direction.
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 25 |