Power
4.1Advanced Configuration and Power Interface (ACPI) States Supported
| This section describes the ACPI states supported by the processor. | |
Table 9. | System States | |
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| State | Description |
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| G0/S0 | Full On Mode. |
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| processor). | |
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| G1/S4 | |
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| G2/S5 | Soft off. All power lost (except wakeup on PCH). Total reboot. |
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| G3 | Mechanical off. All power removed from system. |
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Table 10. | Processor Core / Package State Support | |
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| State | Description |
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| C0 | Active mode, processor executing code. |
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| C1 | AutoHALT state. |
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| C1E | AutoHALT state with lowest frequency and voltage operating point. |
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| C3 | Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache |
| to the L3 shared cache. Clocks are shut off to each core. | |
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| C6 | Execution cores in this state save their architectural state before removing core voltage. |
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| Execution cores in this state behave similarly to the C6 state. If all execution cores |
| C7 | request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is |
| flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3 | |
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| will reduce power consumption. C7 may not be available on all SKUs. |
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Table 11. | Integrated Memory Controller States | |
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| State | Description |
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| Power up | CKE asserted. Active mode. |
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| CKE | |
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| Active Power- | CKE |
| down |
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| CKE | |
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Table 12. | PCI Express* Link States | |
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| State | Description |
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| L0 | Full on – Active transfer state. |
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| L0s | First Active Power Management low power state – Low exit latency. |
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| L1 | Lowest Active Power Management – Longer exit latency. |
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| L3 | Lowest power state |
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| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 49 |