
Table 42. | VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM |
|
| ||||
|
|
|
|
|
|
|
|
| Symbol | Parameter | Typ |
| Max | Units | Notes |
|
|
|
|
|
|
|
|
| VCCIO_OUT | Termination | 1.0 |
| — | V |
|
| Voltage |
|
|
|
| ||
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
| ICCIO_OUT | Maximum | — |
| 300 | mA |
|
|
| External Load |
|
|
|
|
|
|
|
|
|
|
|
|
|
| VCOMP_OUT | Termination | 1.0 |
| — | V | 1 |
|
| Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
| VCCIO_TERM | Termination | 1.0 |
| — | V | 2 |
|
| Voltage |
|
|
|
|
|
|
|
|
|
|
|
| |
| Notes: 1. VCOMP_OUT may only be used to connect to PEG_RCOMP and DP_RCOMP. |
| |||||
| 2. Internal processor power for signal termination. |
|
|
| |||
|
|
|
|
|
|
|
|
Table 43. | DDR3/DDR3L Signal Group DC Specifications |
|
|
|
| |||
|
|
|
|
|
|
|
|
|
| Symbol | Parameter | Min |
| Typ | Max | Units | Notes1 |
| VIL | Input Low Voltage | — |
| VDDQ/2 | 0.43*VDDQ | V | 2, 4, 11 |
| VIH | Input High Voltage | 0.57*VDDQ |
| VDDQ/2 | — | V | 3, 11 |
| VIL | Input Low Voltage | — |
| — | 0.15*VDDQ | V | — |
| (SM_DRAMPWROK) |
| ||||||
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
| VIH | Input High Voltage | 0.45*VDDQ |
| — | 1.0 | V | 10, 12 |
| (SM_DRAMPWROK) |
| ||||||
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Data |
|
|
|
|
|
|
| RON_UP(DQ) | Buffer | 20 |
| 26 | 32 | Ω | 5, 11 |
|
| Resistance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Data |
|
|
|
|
|
|
| RON_DN(DQ) | Buffer | 20 |
| 26 | 32 | Ω | 5, 11 |
|
| Resistance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L |
|
| 50 | 62 | Ω | 11 |
| RODT(DQ) | termination equivalent | 38 |
|
|
|
|
|
| resistance for data |
|
|
|
|
| ||
|
|
|
|
|
|
|
| |
|
| signals |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L | 0.45*VDDQ |
| 0.5*VDDQ | 0.55*VDDQ | V | 11 |
| VODT(DC) | termination DC working |
|
|
|
|
|
|
| point (driver set to |
|
|
|
|
|
| |
|
|
|
|
|
|
|
| |
|
| receive mode) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Clock | 20 |
| 26 | 32 | Ω | 5, 11, |
| RON_UP(CK) | Buffer |
|
|
|
|
| 13 |
|
| Resistance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Clock |
|
|
|
|
| 5, 11, |
| RON_DN(CK) | Buffer | 20 |
| 26 | 32 | Ω | |
|
| 13 | ||||||
|
| Resistance |
|
|
|
|
| |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Command |
|
|
|
|
| 5, 11, |
| RON_UP(CMD) | Buffer | 15 |
| 20 | 25 | Ω | |
|
| 13 | ||||||
|
| Resistance |
|
|
|
|
| |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Command |
|
|
|
|
| 5, 11, |
| RON_DN(CMD) | Buffer | 15 |
| 20 | 25 | Ω | |
|
| 13 | ||||||
|
| Resistance |
|
|
|
|
| |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
| DDR3/DDR3L Control |
|
|
|
|
| 5, 11, |
| RON_UP(CTL) | Buffer | 19 |
| 25 | 31 | Ω | |
|
| 13 | ||||||
|
| Resistance |
|
|
|
|
| |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| continued... |
Intel® Xeon® Processor |
|
Datasheet – Volume 1 of 2 | June 2013 |
96 | Order No.: |