Signal Description—Processor

Signal Name

Description

Direction / Buffer

 

 

Type

 

 

 

 

Clock Enable: (1 per rank). These signals are used to:

 

SB_CKE[3:0]

• Initialize the SDRAMs during power-up.

O

Power-down SDRAM ranks.

DDR3/DDR3L

 

• Place all SDRAM ranks into and out of self-refresh during

 

 

 

STR.

 

 

 

 

 

Chip Select: (1 per rank). These signals are used to select

O

SB_CS#[3:0]

particular SDRAM components during the active state. There is

DDR3/DDR3L

 

one Chip Select for each SDRAM rank.

 

 

 

 

 

SB_ODT[3:0]

On Die Termination: Active Termination Control.

O

 

DDR3/DDR3L

 

 

 

 

 

6.2Memory Reference and Compensation

Table 25.

Memory Reference and Compensation

 

 

 

 

 

 

Signal Name

Description

Direction /

 

 

 

Buffer Type

 

 

 

 

 

SM_RCOMP[2:0]

System Memory Impedance Compensation:

I

 

 

A

 

 

 

 

 

 

 

 

 

DDR3/DDR3L Reference Voltage: This signal is used as

O

 

SM_VREF

a reference voltage to the DDR3/DDR3L controller and is

 

DDR3/DDR3L

 

 

defined as VDDQ/2

 

 

 

 

SA_DIMM_VREFDQ

Memory Channel A/B DIMM DQ Voltage Reference:

O

 

The output pins are connected to the DIMMs, and holds

 

SB_DIMM_VREFDQ

DDR3/DDR3L

 

VDDQ/2 as reference voltage.

 

 

 

 

Intel® Xeon® Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

79