Intel BX80646E31230V3, BX80646E31240V3 6.6Direct Media Interface (DMI), 6.7Phase Locked Loop (PLL) Signals, 6.8Testability Signals

Processor—Signal Description

6.6Direct Media Interface (DMI)

Table 29. Direct Media Interface (DMI) – Processor to PCH Serial Interface

Signal Name	Description	Direction / Buffer
		Type
DMI_RXP[3:0]	DMI Input from PCH: Direct Media Interface receive	I
DMI_RXN[3:0]	differential pair.	DMI
DMI_TXP[3:0]	DMI Output to PCH: Direct Media Interface transmit	O
DMI_TXN[3:0]	differential pair.	DMI

6.7Phase Locked Loop (PLL) Signals

Table 30.	Phase Locked Loop (PLL) Signals
	Signal Name	Description	Direction / Buffer
			Type
	BCLKP	Differential bus clock input to the processor	I
	BCLKN		Diff Clk
	DPLL_REF_CLKP	Embedded Display Port PLL Differential Clock In:	I
	DPLL_REF_CLKN	135 MHz	Diff Clk
	SSC_DPLL_REF_CLKP	Spread Spectrum Embedded DisplayPort PLL	I
	SSC_ DPLL_REF_CLKN	Differential Clock In: 135 MHz	Diff Clk

6.8Testability Signals

Table 31.	Testability Signals
	Signal Name	Description	Direction / Buffer
			Type
		Breakpoint and Performance Monitor Signals:	I/O
	BPM#[7:0]	Outputs from the processor that indicate the status of
		breakpoints and programmable counters used for	CMOS
		monitoring processor performance.
		Debug Reset: This signal is used only in systems where
	DBR#	no debug port is implemented on the system board.	O
		DBR# is used by a debug port interposer so that an in-
		target probe can drive system reset.
		Processor Ready: This signal is a processor output	O
	PRDY#	used by debug tools to determine processor debug
			Asynchronous CMOS
		readiness.
	PREQ#	Processor Request: This signal is used by debug tools	I
		to request debug operation of the processor.	Asynchronous CMOS
		Test Clock: This signal provides the clock input for the	I
	TCK	processor Test Bus (also known as the Test Access
		Port). This signal must be driven low or allowed to float	GTL
		during power on Reset.
		Test Data In: This signal transfers serial test data into	I
	TDI	the processor. This signal provides the serial input
			GTL
		needed for JTAG specification support.
			continued...

Intel® Xeon® Processor E3-1200 v3 Product Family
Datasheet – Volume 1 of 2	June 2013
82	Order No.: 328907-001