6.3Reset and Miscellaneous Signals
Table 26. | Reset and Miscellaneous Signals |
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| Signal Name |
| Description | Direction / |
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| Buffer Type |
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| Configuration Signals: The CFG signals have a default value of |
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| '1' if not terminated on the board. |
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| • CFG[1:0]: Reserved configuration lane. A test point may be |
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| placed on the board for these lanes. |
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| • CFG[2]: PCI Express* Static x16 Lane Numbering Reversal. |
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| — | 1 = Normal operation |
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| — 0 = Lane numbers reversed. |
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| • CFG[3]: MSR Privacy Bit Feature |
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| — 1 = Debug capability is determined by |
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| IA32_Debug_Interface_MSR (C80h) bit[0] setting | I/O |
| CFG[19:0] | — | 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default | |
| GTL | |||
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| setting overridden | |
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| • CFG[4]: Reserved configuration lane. A test point may be |
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| placed on the board for this lane. |
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| • CFG[6:5]: PCI Express* Bifurcation: 1 |
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| — | 00 = 1 x8, 2 x4 PCI Express* |
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| — | 01 = reserved |
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| — | 10 = 2 x8 PCI Express* |
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| — | 11 = 1 x16 PCI Express* |
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| • CFG[19:7]: Reserved configuration lanes. A test point may |
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| be placed on the board for these lands. |
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| CFG_RCOMP | Configuration resistance compensation. Use a 49.9 Ω ±1% | — | |
| resistor to ground. | |||
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| FC (Future Compatibility) signals are signals that are available for |
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| FC_x | compatibility with other processors. A test point may be placed |
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| on the board for these lands. |
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| PM_SYNC | Power Management Sync: A sideband signal to communicate | I | |
| power management status from the platform to the processor. | CMOS | ||
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| PWR_DEBUG# | Signal is for debug. | I | |
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| Asynchronous | |
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| CMOS |
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| IST_TRIGGER | Signal is for IFDIM testing only. | I | |
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| CMOS | |
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| Signal is for debug. If both THERMTRIP# and this signal are | O | |
| IVR_ERROR | simultaneously asserted, the processor has encountered an | ||
| unrecoverable power delivery fault and has engaged automatic | CMOS | ||
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| shutdown as a result. |
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| RESET# | Platform Reset pin driven by the PCH. | I | |
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| CMOS | |
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| RSVD | RESERVED: All signals that are RSVD and RSVD_NCTF must be | No Connect | |
| left unconnected on the board. Intel recommends that all | Test Point | ||
| RSVD_TP | |||
| RSVD_TP signals have via test points. | |||
| RSVD_NCTF |
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| Function | |
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| continued... |
Intel® Xeon® Processor |
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Datasheet – Volume 1 of 2 | June 2013 |
80 | Order No.: |