Power
4.3.4DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports Electrical Power Gating
In C3 or deeper power state, the processor internally gates VDDQ for the majority of the logic to reduce idle power while keeping all critical DDR pins such as SM_DRAMRST#, CKE and VREF in the appropriate state.
In C7, the processor internally gates VCCIO_TERM for all
In S3 or
4.4PCI Express* Power Management
•Active power management is supported using L0s, and L1 states.
•All inputs and outputs disabled in L2/L3 Ready state.
4.5Direct Media Interface (DMI) Power Management
Active power management is supported using L0s/L1 state.
4.6Graphics Power Management
4.6.1Intel® Rapid Memory Power Management (Intel® RMPM)
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
4.6.2Graphics Render C-State
Render
4.6.3Intel® Graphics Dynamic Frequency
Intel Graphics Dynamic Frequency Technology is the ability of the processor and graphics cores to opportunistically increase frequency and/or voltage above the guaranteed processor and graphics frequency for the given part. Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance. The increase in frequency is determined by how much power and thermal budget is available in the
| Intel® Xeon® Processor |
June 2013 | Datasheet – Volume 1 of 2 |
Order No.: | 61 |