Contents
12 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Revision History
Revision Number: 009
Revision Date: 27-Oct-2005
Page# Description
71 Modified Figure 8 “Ethernet Frame Format” [changed Preamble byte count to 7 bytes].
136 Section 45, “RGMII Power” [cha ng ed VCC to V DD in IIH and IIL]
110 Added bullet to Section 5.7.3, “I²C Module C onfiguration Interfac e”: The I2C interface only
supports random single-byte reads and does not guarantee coherency when reading two-byte
registers.
227 Replaced Figure 57 “ FC-PBGA Package (Top and Bot tom Views)” on page 227.
215 Modified Table147 “SPI3 R eceive Configuration ($0 x701)”.
222 Modified Table154 “Optical Module Control Ports 0 - 3 ($0x79A)”: changed default values.
223 Modified Table155 “I2C Control P orts 0 - 3 ($0x79B)”.
249 Modified Table208 “I2C Data Ports 0 - 9 ($0x79F)” (changed address from $0x79C to $0x79F) .
229 Added Section 9.3.3, “Top Label Markin g Example”.
230 Modifed Table157 “Product Information” and Figure 60 “Ordering Information – Sample” unde r
Section 10.0, “Produc t Ordering Information” .
Revision Number: 008
Revision Date: August 1, 2005 (Sheet 1 of 2)
Page# Description
1Added 552-ball Ceramic Ball Grid Array (CBGA) compliant with RoHS and Product Ordering
Number information.
55 Modified Tabl e12 “JTAG Interface S igna l Desc r ip tio ns” : changed Standard to 3.3 V LVTTL from
2.5 V CMOS.
72 Modified Figure 9 “PAUSE Frame Format” [changed Pr eamble byte count to 7 bytes].
85 Modified Figure 11 “MPHY Transmit Logical Timing” [updated TDAT[31:0]].
86 Modified Figure 12 “MPHY Receive Logi cal Timing” [updated RDAT[31:0]].
88 Modified Figure 14 “SPHY T ransmit Logical Timing” [updated TDAT[7:0]].
89 Modified Figure 15 “SPHY Receive Logical Timing” [updated RDAT[7:0] and RPRTY].
121 Modified Figure 31 “Read Timing Diagram - Asynchronous Interface”: changed uPx_ADD [12:0]
to uPx_ADD[10:0].
125 Added paragraphs two and three under Section 5.11, “Loopback Modes”.
129 Changed 3.3 V CMOS to 2.5 V CMOS under Se ction 5.12.5, “JTAG Cloc k” on page 129.
131 Added Section 6.2, “Disable and Enable Port Sequences”.
136 Modified Table45 “RGMII Power” [changed VOH, VOL, VIH, VIL minimum conditions to VDD and
changed VIN value to VDD + .3].
138 Modified Table46 “SPI3 Receiv e Int er fac e Signal Parameters” [chan ged RFCLK duty cycle to
45 min and 55 max; Changed Min for RF CL K frequency to 90].
140 Modified Table47 “SPI3 Transmit Interface Signal Parameters” [changed TFCLK duty cycle to
45 min and 55 max].
146 Changed MDC to MDIO O utput delay max for t3 for 2.5 MHz from 200 to 300 i n Table52 “MDIO
Timing Parameters” on page 146.