Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 218
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
9Rx_port_enable
Port 1
SPHY Mode:
0 = Disables the selected SPI3 RX por t.
1 = Enables the selected S PI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX por t.
1 = Enables the selected S PI3 RX port.
R/W 0x1
8Rx_port_enable
Port 0
SPHY Mode:
0 = Disables the selected SPI3 RX por t.
1 = Enables the selected S PI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX por t.
1 = Enables the selected S PI3 RX port.
R/W 0x1
7 Rx_core_enable
SPHY Mode:
NA. Write as 1, ignore on Read.
MPHY Mode:
0 = Disables the RX SPI3 c ore.
1 = Enables the RX SPI3 c ore.
R/W 0x1
6:1 IBA[5:0]
SPHY Mode:
NA. Write as 0, ignore on Read.
MPHY Mode:
Sets the 6-bit value appe nded to the 2-bit
address during the por t address selection.
R/W 0x00
0 RERR_enable
SPHY Mode/MPHY Mode:
Frames marked to be fil tered (based on the
settings in the “RX Packet Filter Control ($
Port_Index + 0x19)”) or fram e s above the “Max
Frame Size (Addr: Por t_Index + 0x0F)” that are
not dropped in the RX FIFO (see “RX FIFO
Errored Frame Drop Enab le ($0x59F)”can be
optionally indicated wit h an RERR when sent out
the SPI3 interface.
0 = Packets not indicated with RERR.
1 = Packets indicated with RERR.
R/W 0
Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 4 of 4)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write