Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 2 of 2)

Bit

Name

Description

Type1

Default

 

 

 

 

 

3:22

Reserved

Write as 1, ignore on Read.

R/W

11

12

Reserved

Write as 0, ignore on Read.

R/W

0

02

Reserved

Write as 1, ignore on Read.

R/W

1

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

2. Reserved bits must be written to the default value for proper operation.

Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)

Bit

Name

Description

Type1

Default

 

 

 

 

 

Register Description: This register allows for specific packet types to be marked for filtering

 

and is used in conjunction with the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2

0x00000000

- 0x5A5)”.

 

 

 

 

 

 

 

 

31:6

Reserved

Reserved

 

0

 

 

 

 

 

 

 

This bit enables a Global filter on frames with a

 

 

 

 

CRC Error.

 

 

 

 

0 = When CRC Error Pass = 0, all frames with a

 

 

 

 

CRC Error are marked as bad.2

 

 

 

 

1 = Frames with a CRC Error are not marked as

 

 

 

 

bad and are passed to the SPI3 interface for

 

 

 

 

transfer as good frames, regardless of the

 

 

5

CRC Error Pass

state of the bits in the “RX FIFO Errored

R/W

0

Frame Drop Enable ($0x59F)”.

 

 

 

 

 

 

NOTE: When the CRC Error Pass Filter bit = 0, it

 

 

 

 

takes precedence over the other filter bits.

 

 

 

 

Any packet, whether is a Pause, Unicast,

 

 

 

 

Multicast or Broadcast packet with a CRC

 

 

 

 

error, is marked as a bad frame when

 

 

 

 

CRC Error Pass = 0

 

 

 

 

 

 

 

 

 

This bit enables a Global filter on Pause frames.

 

 

 

 

0 = All pause frames are dropped.2

 

 

 

 

1 = All pause frames are passed to the SPI3

 

 

4

Pause Frame Pass

Interface.

R/W

0

 

 

 

NOTE: Pause Frames can only be filtered if

 

 

 

 

RXFD flow control is enabled in the “FC

 

 

 

 

Enable ($ Port_Index + 0x12)”.

 

 

 

 

 

 

 

 

 

This bit enables a global filter on VLAN frames.

 

 

3

VLAN Drop En

0 = All VLAN frames are passed to the SPI3

R/W

0

Interface.

 

 

 

 

 

 

1 = All VLAN frames are dropped.2

 

 

1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

2.Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. This allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be optionally signaled with an RERR (see bit 0 of “SPI3 Receive Configuration ($0x701)”.

Datasheet

172

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

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Intel IXF1104 manual Diverse Config Write $ PortIndex + 0x18 Sheet 2, RX Packet Filter Control $ PortIndex + 0x19 Sheet 1
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IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.
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