Manuals / Intel / Computer Equipment / Switch

Intel IXF1104 manual DC Specifications, Recommended Operating Conditions

Models: IXF1104

1 231

Download 231 pages 58.73 Kb

Page 133

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 40. Recommended Operating Conditions

	Parameter		Symbol	Min	Typ	Max	Units

			VDD	1.65	–	1.95	Volts

			VDD2, VDD3	3.0	–	3.6	Volts

	Recommended supply voltage		VDD4, VDD5	2.3	–	2.7	Volts

			AVDD1P8_1	1.65	–	1.95	Volts
			AVDD1P8_1
			AVDD1P8_2
			AVDD1P8_2

			AVDD2P5_1	2.3	–	2.7	Volts
			AVDD2P5_2	2.3	–	2.7	Volts
			AVDD2P5_2

			VDD
			AVDD1P8_1	–	0.780	–	Amps
		SerDes Operation	AVDD1P8_2
		SerDes Operation
	Operating Current	Transmitting and	VDD4
	Operating Current	receiving in	VDD5
		receiving in	VDD5	–	0.050	–	Amps
		1000 Mbps mode	AVDD2P5_1	–	0.050	–	Amps
		1000 Mbps mode	AVDD2P5_1
			AVDD2P5_2

			VDD2, VDD3	–	0.246	–	Amps

			VDD
			AVDD1P8_1	–	0.757	–	Amps
		RGMII Operation	AVDD1P8_2
		RGMII Operation
	Operating Current	Transmitting and	VDD4
	Operating Current	receiving in	VDD5
		receiving in	VDD5	–	0.224	–	Amps
		1000 Mbps mode	AVDD2P5_1	–	0.224	–	Amps
		1000 Mbps mode	AVDD2P5_1
			AVDD2P5_2

			VDD2, VDD3	–	0.208	0.235	Amps

		Ambient	TOPA	0	–	70	°C

	Recommended	Case with heat	TOPC-HS	0	–	122	°C
	operating	sink	TOPC-HS	0	–	122	°C
	operating	sink
	temperature
	temperature	Case without heat	TOPC-NHS	0	–	121	°C
		Case without heat
		sink
		sink

		SerDes Operation
		Transmitting and	–	–	2.23	2.72	Watts
		receiving in	–	–	2.23	2.72	Watts
		receiving in
	Power	1000 Mbps mode
	Power
	consumption	RGMII Operation
		RGMII Operation
		Transmitting and	–	–	2.84	3.4	Watts
		receiving in	–	–	2.84	3.4	Watts
		receiving in
		1000 Mbps mode

7.1DC Specifications

The IXF1104 MAC supports the following I/O buffer types:

•2.5 V CMOS

•3.3 V LVTTL

•SerDes

133

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Image 133

Intel IXF1104 manual DC Specifications, Recommended Operating Conditions, Parameter Symbol Min Typ Max Units

Contents

Product Features Datasheet Contents 5.1 105 Applications Figures Tables 134 165 198 Revision Number Revision Date 27-Oct-2005 Revision History182 Revision Number Revision Date August 1, 2005 Sheet 2Globally replaced Gbic with Optical Module Interface Revision Date March 24 Revision NumberSheet 2 Modified Txctl Behavior changed signal names Revision Number Revision Date March 24 Sheet 4 # Description Revision Date August 21 Revision Number Revision Date March 24 Sheet 5 DescriptionSheet 1 Initial external release Related Documents What You Will Find in This DocumentDocument General Description Internal Architecture Ball Cbga Assignments Top View Ball AssignmentsBall List in Alphanumeric Order by Signal Name Balls Listed in Alphabetic Order by Signal NameSignal Name Ball Ball List TablesLedclk GND 2CCLKLeddata LedlatchPtpa RxlosintRfclk RMOD0AB5 TxfaultintAD6 AC5UPXDATA6 VDD UPXDATA5 VDDUPXDATA7 VDD UPXDATA8 VDDVDD4 VDD3VDD5 VDD5 AC4 AC8Balls Listed in Alphabetic Order by Ball Location Ball Signal NameBall List in Alphanumeric Order by Ball Location RSX TPRTY1 TDAT9TDAT8 RPRTY1 TPRTY3GND UPXDATA5 VDD GNDVDD VDD5 UPXDATA1 UPXDATA31 UPXDATA11 VDDVDD5 UPXADD7 VDD UPXADD6VDD4 UPXADD8 UPXADD3GND AC2 AC1GND AC3 AC4 VDD5COL2 Datasheet Naming Conventions Ball Assignments and Signal DescriptionsInterface Signals Interface Signal GroupsSPI3 Interface Signal Descriptions Sheet 1 Signal Description TablesSignal Name Ball Type DesignatorSignal Name Ball Type Standard Description SPI3 Interface Signal Descriptions Sheet 2SPI3 Interface Signal Descriptions Sheet 3 DTPA03 Direct Transmit Packet SPI3 Interface Signal Descriptions Sheet 4Available Polled-PHY Transmit Packet Available SPI3 Interface Signal Descriptions Sheet 5Receive Data Bus SPI3 Interface Signal Descriptions Sheet 6 SPI3 Interface Signal Descriptions Sheet 7 SPI3 Interface Signal Descriptions Sheet 8 Signal Name Ball Designator Type Standard Description SerDes Interface Signal DescriptionsTransmit Enable Gmii Interface Signal Descriptions Sheet 1Transmit Data Source Synchronous TransmitReceive Data Gmii Interface Signal Descriptions Sheet 2Carrier Sense Receiver Reference ClockSource Synchronous Transmit Clock Rgmii Interface Signal Descriptions Sheet 1Transmit Control CPU Interface Signal Descriptions Sheet 1 Rgmii Interface Signal Descriptions Sheet 2Receive Control CPU Interface Signal Descriptions Sheet 2 Optical Module Interface Signal Descriptions Sheet 1 Transmit Pause Control Interface Signal DescriptionsSignal Name Ball Type Standard Description Designator Transmit DisableMdio Interface Signal Descriptions Optical Module Interface Signal Descriptions Sheet 2Transmitter Fault Interrupt Module Definition InterruptJtag Interface Signal Descriptions LED Interface Signal DescriptionsSystem Interface Signal Descriptions SysreslAC4 AC8 Power Supply Signal DescriptionsBall Usage Summary Ball Usage SummaryType Quantity Total 552Multiplexed Ball Connections Copper Mode Fiber ModeGMII/RGMII/SerDes/OMI Multiplexed Ball Connections Line Side Interface Multiplexed Balls Sheet 12 SPI3 MPHY/SPHY Ball Connections SPI3 Signals Ball Number CommentsLine Side Interface Multiplexed Balls Sheet 2 SPI3 MPHY/SPHY Interface Sheet 1SPI3 MPHY/SPHY Interface Sheet 2 Interface Ball Name Ball Reset State Comment Ball State During ResetSPI3 MPHY/SPHY Interface Sheet 3 SPI3CPU Jtag TDOLED Leddata GMII/RGMIIPower-Up Sequence Power Supply SequencingPower-Down Sequence Power Supply Power-Up Order Time Delta to Analog Power FilteringPull-Up/Pull-Down Ball Guidelines Pull-Up/Pull-Down and Unused Ball GuidelinesSignal Name Ball Comments Designator Analog Power Supply Filter Network Analog Power BallsFunctional Descriptions Media Access Controller MACPadding of Undersized Frames on Transmit Features for Fiber and Copper ModeAutomatic CRC Generation Filtering of Receive PacketsFilter on Multicast Packet Match Filter CRC Error PacketsFilter Broadcast Packets Filter Vlan PacketsCRC Errored Packets Drop Enable Behavior CRC Error DetectionFlow Control Illustrates the Ieee 802.3 Fifo flow control functions 2.1 802.3x Flow Control Full-Duplex OperationPacket Buffering Fifo Pause Frame Format#%&*#% Pause SettingsTransmit Pause Control Interface Half-Duplex OperationOperation of TX Pause Control Interface Valid Decodes for TXPAUSEADD20Key Configuration Registers ConfigurationMixed-Mode Operation Operational Mode Configuration Registers Fiber ModeRegister Name Description Address Determining If Link Is Established in Auto-Negotiation Mode Copper ModeFiber Forced Mode Determination of Link Establishment in Forced ModeSpeed Jumbo Packet SupportDuplex Copper Auto-NegotiationTX Statistics Rx StatisticsLoss-less Flow Control Rmon Statistics Support Packet Buffer DimensionsTX and RX Fifo Operation TX Fifo RX FifoDefinition of Rmon Rmon Additional Statistics Sheet 1Rmon Ethernet Statistics Type IXF1104 MAC-Equivalent Group 1 StatisticsRmon Additional Statistics Sheet 2 ConventionsRmon Ethernet Statistics Type Advantages SPI3 InterfaceMphy Logical Timing Mphy OperationData Path 1.1 SPI3 RX Round Robin Data TransmissionReceive Timing Transmit TimingLine-Side Interface Network ProcessorMode PortClock Rates Sphy ModeParity Receive Data TransmissionTransmit Timing Sphy Sphy Logical TimingReceive Timing Sphy Sphy Receive Logical Timing SPI3 Bus RX SPI3 Flow Control 2.9 SPI3 Flow ControlTX SPI3 Flow Control Stpa Pre-Pending Function Gigabit Media Independent Interface GmiiGmii Interface Signal Definition Gmii Signal MultiplexingGmii Standard Source Description Gmii Interface Signal DefinitionsTransmit Reference Clock Transmit Data BusMultiplexing of Data and Control Reduced Gigabit Media Independent Interface RgmiiTiming Specifics Rgmii Signal DefinitionsTxer and Rxer Coding Txer and Rxer Coding DescriptionTxctl Behavior 4 10/100 Mbps Functionality Mdio Control and InterfaceIn-Band Status Mdio Address Clear When DoneMdio Register Descriptions MDC GenerationManagement Frames Single MDI Command OperationMDI State Machine MDI State SerDes Interface FeaturesAutoscan Operation Functional DescriptionSerDes Driver TX Power Levels Transmitter Programmable Driver-Power LevelsTransmitter Operational Overview Normalized DRVPWRx3 DRVPWRx2 DRVPWRx1 DRVPWRx0Receiver Operational Overview Selective Power-DownReceiver Jitter Tolerance Receive Jitter Transmit JitterOptical Module Interface SFP Signal Description Signal NamesFunctional Descriptions Low-Speed Status Signaling InterfaceHigh-Speed Serial Interface MODDEF03TXDISABLE03 TXFAULT03Txfaultint RXLOS033.1 I2C Control and Data Registers 3 I²C Module Configuration Interface3.2 I2C Read Operation I2C Random Read Transaction 3.3 I2C Write Operation3.4 I²C Protocol Specifics Start Condition Port Protocol Operation Clock and Data TransitionsStop Condition I2CDataAcknowledge Memory ResetDevice Addressing Random Read OperationModes of Operation LED InterfaceMode 0 Detailed Operation LED Interface Signal DescriptionPin Name Pin # Pin Description Mode 0 Clock Cycle to Data Bit Relationship Mode 1 Detailed OperationLedclk Cycle Leddata DescriptionMode 1 Clock Cycle to Data Bit Relationship Power-On, Reset, InitializationLED Data Decodes Ledclk Cycle Leddata Name Leddata DescriptionLED Behavior Fiber Mode LED Signaling BehaviorFiber LED Behavior LEDDATA# DecodesCPU Interface LED Behavior Copper ModeCopper LED Behavior Write Access Read AccessCPU Timing Parameters EndianTAP State Machine TAP Interface JtagByte Swapper Behavior Little Endian Big EndianInstruction Register Description Instruction Register and Supported InstructionsInstruction Code Description Data Register ID Register Loopback ModesBoundary Scan Register Bypass RegisterSPI3 Interface Loopback Path Line Side Interface LoopbackSystem Interface Reference Clocks ClocksRgmii Clocks 12.2 SPI3 Receive and Transmit ClocksMDC Clock 12.1.1 CLK12512.6 I2C Clock Jtag ClockLED Clock Change Port Mode Initialization Sequence Disable Port Sequence Disable and Enable Port SequencesEnable Port Sequence Absolute Maximum Ratings Parameter Symbol Min Max Units CommentsVDD2, VDD3 TopaParameter Symbol Min Typ Max Units DC SpecificationsRecommended Operating Conditions SerDes Transmit Characteristics Sheet 1 DC SpecificationsParameter Symbol Min Typ Max Units Comments Cmos I/O Cells Normalized ParameterRgmii Electrical Characteristics Undershoot / Overshoot SpecificationsSerDes Transmit Characteristics Sheet 2 SerDes Receive CharacteristicsSymbol Parameter Conditions Min Max Units Rgmii PowerReceive Interface Timing SPI3 AC Timing SpecificationsSymbol Parameter Min Max Units SPI3 Receive Interface Signal ParametersSPI3 Transmit Interface Timing Transmit Interface TimingSPI3 Transmit Interface Signal Parameters Symbol Parameter Min Typ Max Unit Rgmii AC Timing SpecificationRgmii Interface Timing Parameters TXCGmii 1000BASE-T Transmit Signal Parameters Gmii AC Timing Specification1 1000 Base-T Operation 1.1 1000 BASE-T Transmit Interface1.2 1000BASE-T Receive Interface Gmii 1000BASE-T Receive Signal ParametersSerDes Timing Diagram SerDes Timing Parameters SerDes AC Timing SpecificationMDC High-Speed Operation Timing Mdio AC Timing SpecificationMDC Low-Speed Operation Timing Mdio AC Timing Parameter Symbol Min Typ Max Units Test ConditionsMdio Timing Parameters I2C AC Timing Characteristics Sheet 1 Optical Module and I2C AC Timing Specification1 I2C Interface Timing I2C AC Timing Characteristics Sheet 2 CPU Interface Read Cycle AC Timing CPU AC Timing SpecificationCPU Interface Write Cycle AC Timing Symbol Parameter Min Max CPU Interface Write Cycle AC Signal ParametersTransmit Pause Control Interface Timing Parameters Transmit Pause Control AC Timing SpecificationJtag AC Timing Jtag AC Timing Parameters Jtag AC Timing SpecificationSystem Reset AC Timing System Reset AC Timing Parameters System AC Timing SpecificationLED Interface AC Timing Parameters LED AC Timing SpecificationGraphical Representation Document StructurePer Port Registers Register Bit Size Mode OffsetRegister Map MAC Control Registers $ Port Index + Offset Sheet 1MAC RX Statistics Registers $ Port Index + Offset Sheet 1 MAC Control Registers $ Port Index + Offset Sheet 2MAC TX Statistics Registers $ Port Index + Offset MAC RX Statistics Registers $ Port Index + Offset Sheet 2Register Bit Size Mode Address Global Status and Configuration Registers $ 0x500 0X50CPHY Autoscan Registers $ Port Index + Offset RX Fifo Registers $ 0x580 0x5BF Sheet 1TX Fifo Registers $ 0x600 0x63E Sheet 1 RX Fifo Registers $ 0x580 0x5BF Sheet 2TX Fifo Registers $ 0x600 0x63E Sheet 2 SPI3 Receive Configuration $0x701Mdio Registers $ 0x680 SPI3 Registers $ 0x700 0x716 Sheet 1SerDes Registers $ 0x780 SPI3 Registers $ 0x700 0x716 Sheet 2Optical Module Registers $ 0x799 0x79F Station Address $ PortIndex +0x00 +0x01 MAC Control RegistersDesired Duplex $ PortIndex + FD FC Type $ PortIndex +Collision Distance $ PortIndex + FC TX Timer Value $ PortIndex +Collision Threshold $ PortIndex + FD FC Address $ PortIndex + 0x08 +IPG Receive Time 2 $ PortIndex + 0x0B IPG Receive Time 1 $ PortIndex + 0x0AIPG Transmit Time $ PortIndex + 0x0C Max Frame Size Addr PortIndex + 0x0F Pause Threshold $ PortIndex + 0x0EFlush TX $ PortIndex + MAC if Mode and Rgmii Speed $ PortIndex +FC Back Pressure Length $ PortIndex + FC Enable $ PortIndex +TX Hdfc TX FdfcShort Runts Threshold $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 1Discard Unknown Control Frame $ PortIndex + TX Config Word $ PortIndex + 0x17 Sheet 1 RX Config Word $ PortIndex + 0x16 Sheet 2Diverse Config Write $ PortIndex + 0x18 Sheet 1 TX Config Word $ PortIndex + 0x17 Sheet 2RX Packet Filter Control $ PortIndex + 0x19 Sheet 1 Diverse Config Write $ PortIndex + 0x18 Sheet 2Port Multicast Address $ PortIndex +0x1A +0x1B RX Packet Filter Control $ PortIndex + 0x19 Sheet 2MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 1 MAC RX Statistics Register OverviewAddr PortIndex + 0x0F on MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 2Control $ PortIndex + 0x19 is set to MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 3MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 4 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 1 MAC TX Statistics Register OverviewMAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 2 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 3 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 4 PHY Autoscan RegistersPHY Control $ Port Index + 0x60 Sheet 1 PHY Status $ Port Index + 0x61 Sheet 1 PHY Control $ Port Index + 0x60 Sheet 2PHY Identification 1 $ Port Index + PHY Status $ Port Index + 0x61 Sheet 2Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 1 PHY Identification 2 $ Port Index +Asmdir 100BASE-TX10BASE-T Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 2Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 1 Auto-Negotiation Next Page Transmit $ Port Index + Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 2Port Enable $0x500 Global Status and Configuration Register OverviewInterface Mode $0x501 MAC Soft Reset $0x505 Link LED Enable $0x502CPU Interface $0x508 Mdio Soft Reset $0x506LED Control $0x509 LED Flash Rate $0x50A LED Fault Disable $0x50BJedec ID Jtag ID $0x50CRX Fifo High Watermark Port 0 $0x580 RX Fifo Register OverviewRX Fifo High Watermark Port 1 $0x581 RX Fifo High Watermark Port 2 $0x582RX Fifo Low Watermark Port 0 $0x58A RX Fifo High Watermark Port 3 $0x583RX Fifo Low Watermark Port 1 $0x58B RX FifoRX Fifo Low Watermark Port 3 $0x58D RX Fifo Low Watermark Port 2 $0x58CRX Fifo Overflow Frame Drop Counter Ports 0 3 $0x594 RX Fifo Errored Frame Drop Enable $0x59F Sheet 1 RX Fifo Port Reset $0x59ERX Fifo Overflow Event $0x5A0 RX Fifo Errored Frame Drop Enable $0x59F Sheet 2Datasheet 198 RX Fifo SPI3 Loopback Enable for Ports 0 3 $0x5B2 RX Fifo Padding and CRC Strip Enable $0x5B3 RX Fifo Transfer Threshold Port 1 $0x5B9 RX Fifo Transfer Threshold Port 0 $0x5B8RX Fifo Transfer Threshold Port 3 $0x5BB RX Fifo Transfer Threshold Port 2 $0x5BATX Fifo High Watermark Ports 0 3 $0x600 TX Fifo Register OverviewLow watermark for TX Fifo Port 0. TX Fifo Low Watermark Register Ports 0 3 $0x60A 0x60DLow watermark for TX Fifo Port 1. Low watermark for TX Fifo Port 2.MAC threshold for TX Fifo Port 0. TX Fifo MAC Threshold Register Ports 0 3 $0x614MAC threshold for TX Fifo Port 1. MAC threshold for TX Fifo Port 2.Register Description TX Fifo Underflow Event Register Description TX Fifo Out of Sequence EventRegister Description TX Fifo Overflow Event Loop RX Data to TX Fifo Line-Side Loopback Ports 0 3 $0x61F TX Fifo Port Reset $0x620 Sheet 1FOE2 FOE1TX Fifo Overflow Frame Drop Counter Ports 0 3 $0x621 TX Fifo Port Reset $0x620 Sheet 2TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625 TX Fifo Occupancy Counter for Ports 0 3 $0x62D TX Fifo Port Drop Enable $0x63DMdio Register Overview Mdio Single Command $0x680Mdio Single Read and Write Data $0x681 Mdio Control $0x683 Autoscan PHY Address Enable $0x682SPHY/MPHY Mode SPI3 Transmit and Global Configuration $0x700 Sheet 19 SPI3 Register Overview Sphy Mode SPI3 Transmit and Global Configuration $0x700 Sheet 2Mphy Mode Sphy Mode Mphy ModeSPI3 Receive Configuration $0x701 Sheet 1 SPI3 Transmit and Global Configuration $0x700 Sheet 3Bit Name Description Sphy Mode Mphy Mode SPI3 Receive Configuration $0x701 Sheet 2SPI3 Receive Configuration $0x701 Sheet 3 Sphy Mode/MPHY Mode SPI3 Receive Configuration $0x701 Sheet 4Address Parity Error Packet Drop Counter $0x70A TX and RX Power-Down $0x787 TX Driver Power Level Ports 0 3 $0x784RX Signal Detect Level Ports 0 3 $0x793 SerDes Register OverviewPortIndex + 0x10 and the Interface Mode $0x501 Clock and Interface Mode Change Enable Ports 0 3 $0x794Optical Module Status Ports 0-3 $0x799 Optical Module Register OverviewOptical Module Control Ports 0 3 $0x79A I2C Data Ports 0 3 $0x79F I2C Control Ports 0 3 $0x79BPackage Specifics OverviewPackage Information Cbga Package DiagramsCbga Package Side View Diagram FC-PBGA Package Top and Bottom Views Flip Chip-Plastic Ball Grid Array Package DiagramFC-PBGA Mechanical Specifications Package Marking Example Top Label Marking ExampleProduct Number Revision Package RoHS Product InformationHFIXF1104CE.B0 Cbga WFIXF1104CE.B0 PbgaOrdering Information Sample