Manuals / Intel / Computer Equipment / Switch

Intel IXF1104 manual IPG Receive Time 1 $ PortIndex + 0x0A, IPG Receive Time 2 $ PortIndex + 0x0B

Models: IXF1104

1 231
Download 231 pages 58.73 Kb
Page 165
Image 165

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)

Name

Description

Address

Type1

Default

 

 

 

 

 

 

This timer is used during half-duplex operation

 

 

 

 

when there is a packet waiting for

 

 

 

 

transmission from the MAC. This timer starts

 

 

 

 

after CRS is de-asserted. If CRS is asserted

 

 

 

 

during this time, no transmission is initiated

Port_Index

 

 

IPG Receive Time 1

and the counter restarts once CRS is de-

R/W

0x00000008

asserted again.

+ 0x0A

 

 

 

 

The value specified in this register is

 

 

 

 

calculated as follows: (register_value * 8) =

 

 

 

 

RXIPG1 in terms of bit times. Therefore, a

 

 

 

 

default value of 8 gives the following: (8 * 8 =

 

 

 

 

64 bit times for the default).

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)

Name

Description

Address

Type1

Default

 

 

 

 

 

 

This is only used in half-duplex operation. It

 

 

 

 

starts counting at the same time as RXIPG1.

 

 

 

 

Once RXIPG1 expires, a frame is transmitted

 

 

 

 

when RXIPG2 expires regardless of the CRS

 

 

 

 

value. If CRS is asserted before RXIPG1

 

 

 

 

expires, no transmission occurs and both

Port_Index

 

 

IPG Receive Time 2

RXIPG1 an RXIPG2 are reset once CRS is

R/W

0x00000007

+ 0x0B

 

de-asserted again.

 

 

 

 

 

 

 

The value specified in this register is

 

 

 

 

calculated as follows: (register_value +5) * 8 =

 

 

 

 

RXIPG2 in terms of bit times. Therefore, a

 

 

 

 

default of 7 gives the following:

 

 

 

 

(7+5) * 8 = 96 bit times for default.

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 79. IPG Transmit Time ($ Port_Index + 0x0C)

Name

Description

Address

Type1

Default

 

 

 

 

 

 

This is a 10-bit value configuring IPG time for

 

 

 

 

back-to-back transmissions.

 

 

 

 

The value specified in this register is

 

 

 

IPG Transmit Time

calculated as follows: (register_value +4) * 8 =

Port_Index

R/W

0x00000008

TXIPG in terms of bit times. Therefore, a

+ 0x0C

 

 

 

 

default value of 8 gives the following:

 

 

 

 

(8+4) * 8 = 96 bit times for the default.

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

165

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Page 164 Page 166
Page 165
Image 165
Intel IXF1104 manual IPG Receive Time 1 $ PortIndex + 0x0A, IPG Receive Time 2 $ PortIndex + 0x0B
Page 164 Page 166

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.