Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 84. FC Enable ($ Port_Index + 0x12)

Bit

Name

Description

Type1

Default

 

 

 

 

 

Register Description: Indicates which flow control mode is used for the RX and TX MAC.

0x00000007

 

 

 

 

 

31:3

Reserved

Reserved

R

0x00000000

 

 

 

 

 

 

 

When TX HDFC is enabled (half-duplex mode

 

 

 

 

only), the MAC generates deliberate collisions on

 

 

2

TX HDFC

incoming packets when the RX FIFO occupancy

R/W

1

crosses the High Watermark (flow control).

 

 

 

 

 

 

0 = Disable TX half-duplex flow control

 

 

 

 

1 = Enable TX half-duplex flow control

 

 

 

 

 

 

 

 

 

0 = Disable TX full-duplex flow control [the MAC

 

 

 

 

will not generate internally any flow control

 

 

 

 

frames based on the RX FIFO watermarks or

 

 

 

 

the Transmit Pause Control interface

R/W

1

1

TX FDFC

1 = Enable TX full-duplex flow control [enables

 

 

the MAC to send flow control frames to the

 

 

 

 

link partner based on the RX FIFO

 

 

 

 

programmable watermarks or the Transmit

 

 

 

 

Pause Control interface]

 

 

 

 

 

 

 

 

 

0 = Disable RX full-duplex flow control [the MAC

 

 

 

 

will not respond to flow control frames sent to

 

 

 

 

it by the link partner]

 

 

0

RX FDFC

1 = Enable RX full-duplex flow control [MAC will

R/W

1

 

 

respond to flow control frames sent by the link

 

 

 

 

partner and will stop packet transmission for

 

 

 

 

the time specified in the flow control frame]

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 85. FC Back Pressure Length ($ Port_Index + 0x13)

Name

Description

Address

Type1

Default

 

 

 

 

 

 

This register sets number the byte cycles

 

 

 

 

for which the collision has to be applied.

 

 

 

 

The 6-bit configuration holds the value in

 

 

 

FC Back Pressure

bytes, which applies to the minimum

Port Add +

 

 

length/duration of back pressure in half-

R/W

0x0000000C

Length

0x13

duplex mode. Flow control in the receive

 

 

 

 

 

 

 

path is executed by deliberately colliding

 

 

 

 

the incoming packets in half-duplex mode.

 

 

 

 

Register bits 5:0 are used alone.

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet

168

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Page 168
Image 168
Intel IXF1104 manual FC Enable $ PortIndex +, FC Back Pressure Length $ PortIndex +, TX Hdfc, TX Fdfc, RX Fdfc

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.