Intel IXF1104 manual RX Fifo Padding and CRC Strip Enable $0x5B3

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)

Bit	Name	Description		Type1	Default
Register Description: This control register enables to pre-pend every packet with two extra					0x00000000
bytes and also enables the CRC stripping of a packet.
31:8	Reserved	Reserved		RO	0x000000
	CRC Stripping Enable	CRC stripping is enabled for Port 3.
7		0 =	Disabled	R/W	0
	for Port 3
		1 =	Enabled
	CRC Stripping Enable	CRC stripping is enabled for Port 2.
6		0 =	Disabled	R/W	0
	for Port 2
		1 =	Enabled
	CRC Stripping Enable	CRC stripping is enabled for Port 1.
5		0 =	Disabled	R/W	0
	for Port 1
		1 =	Enabled
	CRC Stripping Enable	CRC stripping is enabled for Port 0.
4		0 =	Pre-pending Disabled	R/W	0
	for Port 0
		1 = Pre-pending Enabled
		Enables pre-pending of two bytes at the start of
3	Pre-pending Enable2	every packet – Port 3.		R/W	0
	Port 3	0 =	Disabled
		1 =	Enabled
		Enables pre-pending of two bytes at the start of
2	Pre-pending Enable2	every packet – Port 2.		R/W	0
	Port 2	0 =	Disabled
		1 =	Enabled
		Enables pre-pending of two bytes at the start of
1	Pre-pending Enable2	every packet – Port 1.		R/W	0
	Port 1	0 =	Disabled
		1 =	Enabled
		Enables pre-pending of two bytes at the start of
0	Pre-pending Enable2	every packet – Port 0.		R/W	0
	Port 0	0 =	Disabled
		1 =	Enabled

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

2. Pre-pending should not be enabled in loopback mode.

Datasheet 200

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005