Intel IXF1104 RX Fifo Transfer Threshold Port 2 $0x5BA, RX Fifo Transfer Threshold Port 3 $0x5BB

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)

Bit	Name	Description	Type	Default
Register Description: RX FIFO transfer threshold for port 2 in 8-byte location.				0x000000BE
31:12	Reserved	Reserved	RO	0x00000
		RX FIFO transfer threshold for port 2. This must be
		less than the RX FIFO High water mark.
		User definable control register that sets the
	RX FIFO Transfer	threshold where a packet starts transitioning to the
11:0		SPI3 interface from the RX FIFO before the EOP is	R/W	0x0BE
	Threshold - Port 2	received. Packets received in the RX FIFO below
		this threshold are treated as store and forward.
		NOTE: Do not program the RX FIFO transfer
		threshold below a setting of 0xBE
		(1520bytes).

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)

Bit	Name	Description	Type	Default
Register Description: RX FIFO transfer threshold for port 3 in 8-byte location.				0x000000BE
31:12	Reserved	Reserved	RO	0x00000
		RX FIFO transfer threshold for port 3. This must
		be less than the RX FIFO High water mark.
		User definable control register that sets the
		threshold where a packet starts transitioning to the
11:0	RX FIFO Transfer	SPI3 interface from the RX FIFO before the EOP	R/W	0x0BE
		is received. Packets received in the RX FIFO
	Threshold - Port 3
		below this threshold are treated as store and
		forward.
		NOTE: Do not program the RX FIFO transfer
		threshold below a setting of 0xBE
		(1520bytes).

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet 202

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005