Network Processor, Line-Side Interface, Mode, Port

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Figure 12. MPHYReceive Logical Timing

Figure 13. MPHY 32-Bit Interface

	SPI3 Bus
Network Processor	IXF1104 MPHY	Line-Side Interface
	Mode	Line-Side Interface
	Mode
TFCLK	TFCLK	Transceiver
TENB	TENB_0	Transceiver
TENB	TENB_0	Port 0
TDAT[31:0]	TDAT[31:0]
TMOD[1:0]	TMOD[1:0]
TPRTY	TPRTY_0
TSOP	TSOP_0
TEOP	TEOP_0	Transceiver
TERR	TERR_0	Port 1
TERR	TERR_0
TSX	TSX
DTPA_0:3	DTPA_0:3
STPA	STPA	Transceiver
PTPA	PTPA	Transceiver
PTPA	PTPA	Port 2
TADR[1:0]	TADR[1:0]	Port 2
TADR[1:0]	TADR[1:0]
RFCLK	RFCLK
RENB	RENB_0
RDAT[31:0]	RDAT[31:0]	Transceiver
RMOD[1:0]	RMOD[1:0]	Port 3
RPRTY	RPRTY_0
RVAL	RVAL_0
RSOP	RSOP_0
REOP	REOP_0
RERR	RERR_0
RSX	RSX
		B0660-02
Datasheet		86

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Page 86

Image 86

Intel IXF1104 manual Network Processor, Line-Side Interface, Mode, Port

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.

Contents

Product Features Datasheet Contents 5.1 105 Applications Figures Tables 134 165 198 Revision History Revision Number Revision Date 27-Oct-2005 Revision Number Revision Date August 1, 2005 Sheet 2 182 Globally replaced Gbic with Optical Module Interface Sheet 2 Revision NumberRevision Date March 24 Modified Txctl Behavior changed signal names Revision Number Revision Date March 24 Sheet 4 # Description Sheet 1 Revision Number Revision Date March 24 Sheet 5 DescriptionRevision Date August 21 Initial external release Document What You Will Find in This DocumentRelated Documents General Description Internal Architecture Ball Assignments Ball Cbga Assignments Top View Signal Name Ball Balls Listed in Alphabetic Order by Signal NameBall List in Alphanumeric Order by Signal Name Ball List Tables Leddata GND 2CCLKLedclk Ledlatch Rfclk RxlosintPtpa RMOD0 AD6 TxfaultintAB5 AC5 UPXDATA7 VDD UPXDATA5 VDDUPXDATA6 VDD UPXDATA8 VDD VDD5 VDD3VDD4 VDD5 AC4 AC8 Ball List in Alphanumeric Order by Ball Location Ball Signal NameBalls Listed in Alphabetic Order by Ball Location TDAT8 TDAT9RSX TPRTY1 RPRTY1 TPRTY3 VDD VDD5 UPXDATA1 VDD GNDGND UPXDATA5 UPXDATA31 UPXDATA11 VDD VDD4 UPXADD8 VDD UPXADD6VDD5 UPXADD7 UPXADD3 GND AC3 AC1GND AC2 AC4 VDD5 COL2 Datasheet Ball Assignments and Signal Descriptions Naming Conventions Interface Signal Groups Interface Signals Signal Name Ball Type Signal Description TablesSPI3 Interface Signal Descriptions Sheet 1 Designator SPI3 Interface Signal Descriptions Sheet 2 Signal Name Ball Type Standard Description SPI3 Interface Signal Descriptions Sheet 3 Available SPI3 Interface Signal Descriptions Sheet 4DTPA03 Direct Transmit Packet Receive Data Bus SPI3 Interface Signal Descriptions Sheet 5Polled-PHY Transmit Packet Available SPI3 Interface Signal Descriptions Sheet 6 SPI3 Interface Signal Descriptions Sheet 7 SPI3 Interface Signal Descriptions Sheet 8 SerDes Interface Signal Descriptions Signal Name Ball Designator Type Standard Description Transmit Data Gmii Interface Signal Descriptions Sheet 1Transmit Enable Source Synchronous Transmit Carrier Sense Gmii Interface Signal Descriptions Sheet 2Receive Data Receiver Reference Clock Transmit Control Rgmii Interface Signal Descriptions Sheet 1Source Synchronous Transmit Clock Receive Control Rgmii Interface Signal Descriptions Sheet 2CPU Interface Signal Descriptions Sheet 1 CPU Interface Signal Descriptions Sheet 2 Signal Name Ball Type Standard Description Designator Transmit Pause Control Interface Signal DescriptionsOptical Module Interface Signal Descriptions Sheet 1 Transmit Disable Transmitter Fault Interrupt Optical Module Interface Signal Descriptions Sheet 2Mdio Interface Signal Descriptions Module Definition Interrupt System Interface Signal Descriptions LED Interface Signal DescriptionsJtag Interface Signal Descriptions Sysresl Power Supply Signal Descriptions AC4 AC8 Type Quantity Ball Usage SummaryBall Usage Summary Total 552 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections Copper Mode Fiber ModeMultiplexed Ball Connections Line Side Interface Multiplexed Balls Sheet 1 Line Side Interface Multiplexed Balls Sheet 2 SPI3 Signals Ball Number Comments2 SPI3 MPHY/SPHY Ball Connections SPI3 MPHY/SPHY Interface Sheet 1 SPI3 MPHY/SPHY Interface Sheet 2 SPI3 MPHY/SPHY Interface Sheet 3 Ball State During ResetInterface Ball Name Ball Reset State Comment SPI3 LED Leddata Jtag TDOCPU GMII/RGMII Power-Down Sequence Power Supply SequencingPower-Up Sequence Pull-Up/Pull-Down Ball Guidelines Analog Power FilteringPower Supply Power-Up Order Time Delta to Pull-Up/Pull-Down and Unused Ball Guidelines Analog Power Supply Filter Network Analog Power Balls Signal Name Ball Comments Designator Media Access Controller MAC Functional Descriptions Automatic CRC Generation Features for Fiber and Copper ModePadding of Undersized Frames on Transmit Filtering of Receive Packets Filter Broadcast Packets Filter CRC Error PacketsFilter on Multicast Packet Match Filter Vlan Packets Flow Control CRC Error DetectionCRC Errored Packets Drop Enable Behavior 2.1 802.3x Flow Control Full-Duplex Operation Illustrates the Ieee 802.3 Fifo flow control functions Pause Frame Format Packet Buffering Fifo Pause Settings #%&*#% Half-Duplex Operation Transmit Pause Control Interface Valid Decodes for TXPAUSEADD20 Operation of TX Pause Control Interface Mixed-Mode Operation ConfigurationKey Configuration Registers Register Name Description Address Fiber ModeOperational Mode Configuration Registers Fiber Forced Mode Copper ModeDetermining If Link Is Established in Auto-Negotiation Mode Determination of Link Establishment in Forced Mode Duplex Jumbo Packet SupportSpeed Copper Auto-Negotiation Loss-less Flow Control Rx StatisticsTX Statistics TX and RX Fifo Operation TX Fifo Packet Buffer DimensionsRmon Statistics Support RX Fifo Rmon Ethernet Statistics Type IXF1104 MAC-Equivalent Rmon Additional Statistics Sheet 1Definition of Rmon Group 1 Statistics Rmon Ethernet Statistics Type ConventionsRmon Additional Statistics Sheet 2 SPI3 Interface Advantages Data Path Mphy OperationMphy Logical Timing 1.1 SPI3 RX Round Robin Data Transmission Transmit Timing Receive Timing Mode Network ProcessorLine-Side Interface Port Parity Sphy ModeClock Rates Receive Data Transmission Receive Timing Sphy Sphy Logical TimingTransmit Timing Sphy Sphy Receive Logical Timing SPI3 Bus TX SPI3 Flow Control 2.9 SPI3 Flow ControlRX SPI3 Flow Control Stpa Gigabit Media Independent Interface Gmii Pre-Pending Function Gmii Signal Multiplexing Gmii Interface Signal Definition Transmit Reference Clock Gmii Interface Signal DefinitionsGmii Standard Source Description Transmit Data Bus Reduced Gigabit Media Independent Interface Rgmii Multiplexing of Data and Control Txer and Rxer Coding Rgmii Signal DefinitionsTiming Specifics Txer and Rxer Coding Description Txctl Behavior In-Band Status Mdio Control and Interface4 10/100 Mbps Functionality Mdio Register Descriptions Clear When DoneMdio Address MDC Generation MDI State Machine Single MDI Command OperationManagement Frames MDI State Autoscan Operation FeaturesSerDes Interface Functional Description Transmitter Operational Overview Transmitter Programmable Driver-Power LevelsSerDes Driver TX Power Levels Normalized DRVPWRx3 DRVPWRx2 DRVPWRx1 DRVPWRx0 Receiver Jitter Tolerance Selective Power-DownReceiver Operational Overview Transmit Jitter Receive Jitter SFP Signal Description Signal Names Optical Module Interface High-Speed Serial Interface Low-Speed Status Signaling InterfaceFunctional Descriptions MODDEF03 Txfaultint TXFAULT03TXDISABLE03 RXLOS03 3.2 I2C Read Operation 3 I²C Module Configuration Interface3.1 I2C Control and Data Registers 3.3 I2C Write Operation I2C Random Read Transaction 3.4 I²C Protocol Specifics Stop Condition Port Protocol Operation Clock and Data TransitionsStart Condition I2CData Device Addressing Memory ResetAcknowledge Random Read Operation LED Interface Modes of Operation Pin Name Pin # Pin Description LED Interface Signal DescriptionMode 0 Detailed Operation Ledclk Cycle Mode 1 Detailed OperationMode 0 Clock Cycle to Data Bit Relationship Leddata Description LED Data Decodes Power-On, Reset, InitializationMode 1 Clock Cycle to Data Bit Relationship Ledclk Cycle Leddata Name Leddata Description Fiber LED Behavior LED Signaling BehaviorLED Behavior Fiber Mode LEDDATA# Decodes Copper LED Behavior LED Behavior Copper ModeCPU Interface Read Access Write Access Endian CPU Timing Parameters Byte Swapper Behavior TAP Interface JtagTAP State Machine Little Endian Big Endian Instruction Code Description Data Register Instruction Register and Supported InstructionsInstruction Register Description Boundary Scan Register Loopback ModesID Register Bypass Register Line Side Interface Loopback SPI3 Interface Loopback Path Clocks System Interface Reference Clocks MDC Clock 12.2 SPI3 Receive and Transmit ClocksRgmii Clocks 12.1.1 CLK125 LED Clock Jtag Clock12.6 I2C Clock Change Port Mode Initialization Sequence Enable Port Sequence Disable and Enable Port SequencesDisable Port Sequence VDD2, VDD3 Parameter Symbol Min Max Units CommentsAbsolute Maximum Ratings Topa Recommended Operating Conditions DC SpecificationsParameter Symbol Min Typ Max Units Parameter Symbol Min Typ Max Units Comments Cmos I/O Cells DC SpecificationsSerDes Transmit Characteristics Sheet 1 Normalized Parameter SerDes Transmit Characteristics Sheet 2 Undershoot / Overshoot SpecificationsRgmii Electrical Characteristics SerDes Receive Characteristics Rgmii Power Symbol Parameter Conditions Min Max Units SPI3 AC Timing Specifications Receive Interface Timing SPI3 Receive Interface Signal Parameters Symbol Parameter Min Max Units Transmit Interface Timing SPI3 Transmit Interface Timing SPI3 Transmit Interface Signal Parameters Rgmii Interface Timing Parameters Rgmii AC Timing SpecificationSymbol Parameter Min Typ Max Unit TXC 1 1000 Base-T Operation Gmii AC Timing SpecificationGmii 1000BASE-T Transmit Signal Parameters 1.1 1000 BASE-T Transmit Interface Gmii 1000BASE-T Receive Signal Parameters 1.2 1000BASE-T Receive Interface SerDes AC Timing Specification SerDes Timing Diagram SerDes Timing Parameters MDC Low-Speed Operation Timing Mdio AC Timing SpecificationMDC High-Speed Operation Timing Mdio Timing Parameters Parameter Symbol Min Typ Max Units Test ConditionsMdio AC Timing 1 I2C Interface Timing Optical Module and I2C AC Timing SpecificationI2C AC Timing Characteristics Sheet 1 I2C AC Timing Characteristics Sheet 2 CPU Interface Write Cycle AC Timing CPU AC Timing SpecificationCPU Interface Read Cycle AC Timing CPU Interface Write Cycle AC Signal Parameters Symbol Parameter Min Max Transmit Pause Control AC Timing Specification Transmit Pause Control Interface Timing Parameters Jtag AC Timing Specification Jtag AC Timing Jtag AC Timing Parameters System AC Timing Specification System Reset AC Timing System Reset AC Timing Parameters LED AC Timing Specification LED Interface AC Timing Parameters Document Structure Graphical Representation Register Map Register Bit Size Mode OffsetPer Port Registers MAC Control Registers $ Port Index + Offset Sheet 1 MAC Control Registers $ Port Index + Offset Sheet 2 MAC RX Statistics Registers $ Port Index + Offset Sheet 1 MAC RX Statistics Registers $ Port Index + Offset Sheet 2 MAC TX Statistics Registers $ Port Index + Offset PHY Autoscan Registers $ Port Index + Offset Global Status and Configuration Registers $ 0x500 0X50CRegister Bit Size Mode Address RX Fifo Registers $ 0x580 0x5BF Sheet 1 RX Fifo Registers $ 0x580 0x5BF Sheet 2 TX Fifo Registers $ 0x600 0x63E Sheet 1 Mdio Registers $ 0x680 SPI3 Receive Configuration $0x701TX Fifo Registers $ 0x600 0x63E Sheet 2 SPI3 Registers $ 0x700 0x716 Sheet 1 Optical Module Registers $ 0x799 0x79F SPI3 Registers $ 0x700 0x716 Sheet 2SerDes Registers $ 0x780 Desired Duplex $ PortIndex + MAC Control RegistersStation Address $ PortIndex +0x00 +0x01 FD FC Type $ PortIndex + Collision Threshold $ PortIndex + FC TX Timer Value $ PortIndex +Collision Distance $ PortIndex + FD FC Address $ PortIndex + 0x08 + IPG Transmit Time $ PortIndex + 0x0C IPG Receive Time 1 $ PortIndex + 0x0AIPG Receive Time 2 $ PortIndex + 0x0B Pause Threshold $ PortIndex + 0x0E Max Frame Size Addr PortIndex + 0x0F MAC if Mode and Rgmii Speed $ PortIndex + Flush TX $ PortIndex + TX Hdfc FC Enable $ PortIndex +FC Back Pressure Length $ PortIndex + TX Fdfc Discard Unknown Control Frame $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 1Short Runts Threshold $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 2 TX Config Word $ PortIndex + 0x17 Sheet 1 TX Config Word $ PortIndex + 0x17 Sheet 2 Diverse Config Write $ PortIndex + 0x18 Sheet 1 Diverse Config Write $ PortIndex + 0x18 Sheet 2 RX Packet Filter Control $ PortIndex + 0x19 Sheet 1 RX Packet Filter Control $ PortIndex + 0x19 Sheet 2 Port Multicast Address $ PortIndex +0x1A +0x1B MAC RX Statistics Register Overview MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 1 MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 2 Addr PortIndex + 0x0F on MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 3 Control $ PortIndex + 0x19 is set to MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 4 MAC TX Statistics Register Overview MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 1 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 2 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 3 PHY Control $ Port Index + 0x60 Sheet 1 PHY Autoscan RegistersMAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 4 PHY Control $ Port Index + 0x60 Sheet 2 PHY Status $ Port Index + 0x61 Sheet 1 PHY Status $ Port Index + 0x61 Sheet 2 PHY Identification 1 $ Port Index + Asmdir PHY Identification 2 $ Port Index +Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 1 100BASE-TX Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 2 10BASE-T Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 1 Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 2 Auto-Negotiation Next Page Transmit $ Port Index + Interface Mode $0x501 Global Status and Configuration Register OverviewPort Enable $0x500 Link LED Enable $0x502 MAC Soft Reset $0x505 LED Control $0x509 Mdio Soft Reset $0x506CPU Interface $0x508 LED Fault Disable $0x50B LED Flash Rate $0x50A Jtag ID $0x50C Jedec ID RX Fifo High Watermark Port 1 $0x581 RX Fifo Register OverviewRX Fifo High Watermark Port 0 $0x580 RX Fifo High Watermark Port 2 $0x582 RX Fifo Low Watermark Port 1 $0x58B RX Fifo High Watermark Port 3 $0x583RX Fifo Low Watermark Port 0 $0x58A RX Fifo RX Fifo Overflow Frame Drop Counter Ports 0 3 $0x594 RX Fifo Low Watermark Port 2 $0x58CRX Fifo Low Watermark Port 3 $0x58D RX Fifo Port Reset $0x59E RX Fifo Errored Frame Drop Enable $0x59F Sheet 1 RX Fifo Errored Frame Drop Enable $0x59F Sheet 2 RX Fifo Overflow Event $0x5A0 Datasheet 198 RX Fifo SPI3 Loopback Enable for Ports 0 3 $0x5B2 RX Fifo Padding and CRC Strip Enable $0x5B3 RX Fifo Transfer Threshold Port 0 $0x5B8 RX Fifo Transfer Threshold Port 1 $0x5B9 RX Fifo Transfer Threshold Port 2 $0x5BA RX Fifo Transfer Threshold Port 3 $0x5BB TX Fifo Register Overview TX Fifo High Watermark Ports 0 3 $0x600 Low watermark for TX Fifo Port 1. TX Fifo Low Watermark Register Ports 0 3 $0x60A 0x60DLow watermark for TX Fifo Port 0. Low watermark for TX Fifo Port 2. MAC threshold for TX Fifo Port 1. TX Fifo MAC Threshold Register Ports 0 3 $0x614MAC threshold for TX Fifo Port 0. MAC threshold for TX Fifo Port 2. Register Description TX Fifo Overflow Event Register Description TX Fifo Out of Sequence EventRegister Description TX Fifo Underflow Event FOE2 TX Fifo Port Reset $0x620 Sheet 1Loop RX Data to TX Fifo Line-Side Loopback Ports 0 3 $0x61F FOE1 TX Fifo Port Reset $0x620 Sheet 2 TX Fifo Overflow Frame Drop Counter Ports 0 3 $0x621 TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625 TX Fifo Port Drop Enable $0x63D TX Fifo Occupancy Counter for Ports 0 3 $0x62D Mdio Single Read and Write Data $0x681 Mdio Single Command $0x680Mdio Register Overview Autoscan PHY Address Enable $0x682 Mdio Control $0x683 9 SPI3 Register Overview SPI3 Transmit and Global Configuration $0x700 Sheet 1SPHY/MPHY Mode Mphy Mode Sphy Mode SPI3 Transmit and Global Configuration $0x700 Sheet 2Sphy Mode Mphy Mode Bit Name Description SPI3 Transmit and Global Configuration $0x700 Sheet 3SPI3 Receive Configuration $0x701 Sheet 1 SPI3 Receive Configuration $0x701 Sheet 2 Sphy Mode Mphy Mode SPI3 Receive Configuration $0x701 Sheet 3 SPI3 Receive Configuration $0x701 Sheet 4 Sphy Mode/MPHY Mode Address Parity Error Packet Drop Counter $0x70A RX Signal Detect Level Ports 0 3 $0x793 TX Driver Power Level Ports 0 3 $0x784TX and RX Power-Down $0x787 SerDes Register Overview Clock and Interface Mode Change Enable Ports 0 3 $0x794 PortIndex + 0x10 and the Interface Mode $0x501 Optical Module Control Ports 0 3 $0x79A Optical Module Register OverviewOptical Module Status Ports 0-3 $0x799 I2C Control Ports 0 3 $0x79B I2C Data Ports 0 3 $0x79F Overview Package Specifics Cbga Package Diagrams Package Information Cbga Package Side View Diagram Flip Chip-Plastic Ball Grid Array Package Diagram FC-PBGA Package Top and Bottom Views FC-PBGA Mechanical Specifications Top Label Marking Example Package Marking Example HFIXF1104CE.B0 Cbga WFIXF1104CE.B0 Product InformationProduct Number Revision Package RoHS Pbga Ordering Information Sample

Figure 12. MPHY￿￿￿￿￿Receive Logical Timing

Figure 13. MPHY 32-Bit Interface

Network Processor

IXF1104 MPHY

Line-Side Interface

Mode

Port 0

Datasheet

Document Number: 278757

IXF1104 specifications

Figure 12. MPHYReceive Logical Timing