Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 38
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
4.2 Interface Signal Groups
This section describes the IXF1104 MAC signals in groups according to th e associated interface or
function. Figure 4 shows the various interfaces available on the IXF1104 MAC.
Figure 4. Interface Signals
TDAT[ 31: 0]
TFCLK
TENB_0
TERR_0
TPRTY_0
TMOD[1:0]
TSX
TSOP_0
TEOP_0
TADR[1:0]
DTPA_0:3
STPA
PTPA
RDAT [ 31: 0]
RFCLK
RENB_0
RVAL_0
RERR_0
RPRTY_0
RMOD[1:0]
RSX
RSOP_0
REOP_0
TMS
TDI
TDO
TCLK
MDIO
MDC
TXPAUSEADD [2:0]
TXPAUSEFR
UPX_WIDTH[1:0]
UPX_DA TA [ 31:0 ]
UPX_ADD[10: 0]
UPX_BADD[1: 0]
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_RDY_L
LED_CLK
LED_DATA
LED_LATC H
SYS_RES_L
CLK125
MOD_DEF_0:3
TX_DIS ABL E_0: 3
TX_FAU LT_ 0:3
RX_LOS_0: 3
TX_FAU LT_ IN T
RX_LOS_I N T
MOD_DEF_IN T
I
2
C_CLK
I
2
C_DATA_0:3
SPI3
Interface
JTAG
Interface
MDIO
Interface
Pause
Control
Interface
CPU
Interface
LED
Interface
System
Interface
GMII RGMII
GMII and
RGMII
Interfaces*
* Data and cl oc k balls are shar ed f or
GMII and RGMII Interfaces
SerDes
Interface
Optical
Module
Interface
Signal s*
*
** These optic a l m odule signals
are multiplexed on the GM I I balls.
RX_P/N_0:3
TX_P/N_0:3
TRST_L
Intel
®
IXF1104
Media Access
Controller
B3181-01
MPHYSPHY
TFCLK
TENB_0: 3
TERR _0: 3
TPRTY _0: 3
TSOP_0:3
TEOP_0:3
TDAT[7:0]_0:3
TADR[1:0]
DTPA_0: 3
PTPA
RDAT[7:0]_0:3
RFCLK
RENB_0:3
RVAL_0:3
RERR_0:3
RPRTY_0:3
RSOP_0: 3
REOP_0: 3
TXC_0:3
TXD[7: 0] _3
TXC_0: 3
TD[3:0]_3
TXD[7: 0] _2 TD[3: 0] _2
TXD[7: 0] _1 TD[3: 0] _1
TXD[7: 0] _0 TD[3:0]_0
TX_EN_0:3
TX_ER_0:3
TX_CTL _0: 3
RXC_0: 3 RXC_0: 3
RXD[7:0]_3
RD[3:0]_3
RXD[7:0]_2
RD[3:0]_2RXD[7:0]_1
RD[3:0]_1
RXD[7:0]_0
RD[3:0]_0
RX_DV_ 0:3
RX_ER_0:3
CRS_0:3
COL_0:3
RX_CT L_0: 3