Intel IXF1104 manual SPI3 MPHY/SPHY Interface Sheet 2

Models: IXF1104

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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)

SPI3 Signals

 

Ball Number

 

Comments

 

 

 

 

MPHY

SPHY

 

 

 

 

 

 

 

 

 

 

 

 

TERR_0

TERR_0

A8

 

 

 

MPHY: Use TERR_0 as the TERR

 

 

 

 

 

 

GND

TERR_1

K1

 

 

 

 

 

 

signal.

 

 

 

 

 

 

SPHY: Each port has its own dedicated

GND

TERR_2

E11

 

 

 

 

 

 

 

 

 

TERR_n signal

GND

TERR_3

J8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TSOP_0

TSOP_0

C7

 

 

 

MPHY: Use TSOP_0 as the TSOP

 

 

 

 

 

 

GND

TSOP_1

E3

 

 

 

 

 

 

signal.

 

 

 

 

 

 

SPHY: Each port has a dedicated

GND

TSOP_2

C10

 

 

 

 

 

 

 

 

 

TSOP_n signal.

GND

TSOP_3

J5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEOP_0

TEOP_0

A7

 

 

 

MPHY: Use TEOP_0 as the TEOP

 

 

 

 

 

 

GND

TEOP_1

F3

 

 

 

 

 

 

signal.

 

 

 

 

 

 

SPHY: Each port has a dedicated

GND

TEOP_2

E4

 

 

 

 

 

 

 

 

 

TEOP_n signal.

GND

TEOP_3

H5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMOD[1:0]

GND

D9

A6

 

 

TSX and TMOD[1:0] are only applicable

 

 

 

 

 

 

TSX

GND

E1

 

 

 

in MPHY mode.

 

 

 

 

 

 

 

 

 

 

 

TADR[1:0]

TADR[1:0]

A12

A11

 

 

Used to address port for PTPA signal.

 

 

 

 

 

 

 

PTPA

PTPA

B11

 

 

 

PTPA can be used in MPHY and SPHY

 

 

 

modes.

 

 

 

 

 

 

 

 

 

 

 

 

 

DTPA_0:3

DTPA_0:3

D3

L1

A9

J7

DTPA is available on a per-port basis in

both MPHY and SPHY modes.

 

 

 

 

 

 

 

 

 

 

 

 

 

STPA

NC

C11

 

 

 

STPA is only applicable in MPHY mode.

 

 

 

 

 

 

 

RDAT[31:24]

RDAT[7:0]_3

F24

G24

G23

G22

 

G21

G20

G19

G18

 

 

 

 

 

 

 

 

 

 

 

RDAT[23:16]

RDAT[7:0]_2

E21

E22

D22

C22

MPHY: Consists of a single 32 bit data

C21

C20

B22

B20

bus.

 

 

 

 

 

 

 

 

SPHY: Separate 8-bit data bus for each

RDAT[15:8]

RDAT[7:0]_1

F18

E18

E17

F16

E16

D16

C17

A17

Ethernet port.

 

 

 

 

 

 

 

 

 

RDAT[7:0]

RDAT[7:0]_0

F14

E14

D14

C13

 

C14

B14

A15

A14,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

To achieve maximum bandwidth, set

RFCLK

RFCLK

A19

 

 

 

RFCLK as follows:

 

 

 

MPHY: 133 MHz.

 

 

 

 

 

 

 

 

 

 

 

 

SPHY: 125 MHz.

 

 

 

 

 

 

 

RPRTY_0

RPRTY_0

E15

 

 

 

MPHY: Use RPRTY_0 as the RPRTY

 

 

 

 

 

 

NC

RPRTY_1

G16

 

 

 

 

 

 

signal.

 

 

 

 

 

 

SPHY: Each port has a dedicated

NC

RPRTY_2

E20

 

 

 

 

 

 

 

 

 

RPRTY_n signal.

NC

RPRTY_3

F20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RENB_0

RENB_0

A13

 

 

 

MPHY: Use RENB_0 as the RENB

 

 

 

 

 

 

VDD2

RENB_1

A18

 

 

 

 

 

 

signal.

 

 

 

 

 

 

SPHY: Each port has a dedicated

VDD2

RENB_2

C19

 

 

 

 

 

 

 

 

 

RENB_n signal

VDD2

RENB_3

E24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Datasheet

60

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Page 60
Image 60
Intel IXF1104 manual SPI3 MPHY/SPHY Interface Sheet 2

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.