Intel IXF1104 manual 3.3 I2C Write Operation, I2C Random Read Transaction

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

1.Initialize the Control register by setting the following values:

a.Enable the I2C Controller by setting bit [25] to 0x1.

b.Initiate the I2C transfer by setting bit [24] of the control register to 0x1.

c.Select the port by using bits [17:16].

d.Select the Read mode of operation by setting bit [15] to 0x1.

e.Select the Device ID by setting bits [14:11].

f.Select the register address by setting bits [10:0].

2.Set the Device ID field to 0xA and the register address (bits 10:8) to 0x0 to access the fiber module serial E2PROM. Setting the Device ID field to 0xA and the Register Address [10:8] to 0x0 permits read-only access.

3.Set the Device ID field to 0xA and the Register Address [10:8] between the values of 0x1 and 0x7 to access the PHY registers.

4.Poll the Read_Valid field, bit 20. The read data is available when this bit is set to 0x1.

Figure 24 shows an 8-bit read access.

Note: The user software ensures the order of the contiguous accesses required to read the High and Low bytes of 16-bit-wide PHY registers.

Figure 24. I2C Random Read Transaction

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I2C_Data Line

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DUMMY WRITE

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(* = DON'T CARE bit for1k)

Note: Only one optical module I²C access sequence can be run at any given time. If a second write is carried out to the “I2C Control Ports 0 - 3 ($0x79B)" and “I2C Data Ports 0 - 3 ($0x79F)" before a result is returned for the previous write, the data for the first write is lost. An internal state machine completes the Optical Module Interface register access for the first write. It attempts to place the data in the DataRead field and checks to see if the WriteCommand bit is 00h. If it is not 00h, it discards the data and signals the I²C access state machine to begin a new cycle using the data from the second write.

5.7.3.3I2C Write Operation

The following sequence provides an example of writing data to Register Address 0xFF for Port 3:

1.Program the “I2C Control Ports 0 - 3 ($0x79B)" with the following information: a. Enable the I2C block by setting Register bit 25 to 0x1.

111 Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005