Manuals / Intel / Computer Equipment / Switch

Intel IXF1104 manual Gmii AC Timing Specification, 1 1000 Base-T Operation

Models: IXF1104

1 231

Download 231 pages 58.73 Kb

Page 142

Image 142

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

7.4GMII AC Timing Specification

7.4.11000 Base-T Operation

Figure 38 and Figure 39 and Table 49 and Table 50 provide GMII AC timing specifications.

7.4.1.11000 BASE-T Transmit Interface

Figure 38. 1000BASE-T Transmit Interface Timing

GTX_CLK
TXEn
t1	t2
TXD[7:0]
TXER
t3
CPS	t4
	t4
	B0634-01

Table 49. GMII 1000BASE-T Transmit Signal Parameters

Symbol		Parameter	Min	Typ1	Max	Unit2

	t1	TXD[7:0], TXEN, TXER Set-up to TXC High	2.5	–	–	ns

	t2	TXD[7:0], TXEN, TXER Hold from TXC High	0.5	–	–	ns

	t3	TXEN sampled to CRS asserted	–	–	16	BT

	t4	TXEN sampled to CRS de-asserted	–	–	16	BT

1.	Typical values are at 25oC and are for design aid only; not guaranteed and not subject to production
	testing.
2.	Bit Time (BT) is the duration of one bit as transferred to/from the PHY and is the reciprocal of bit rate. BT for
	1000BASE-T = 10-9or 1 ns.

Datasheet

142

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

Page 142

Image 142

Intel IXF1104 manual Gmii AC Timing Specification, 1 1000 Base-T Operation, 1.1 1000 BASE-T Transmit Interface

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.

Contents

Product Features Datasheet Contents 5.1 105 Applications Figures Tables 134 165 198 Revision History Revision Number Revision Date 27-Oct-2005Revision Number Revision Date August 1, 2005 Sheet 2 182Globally replaced Gbic with Optical Module Interface Revision Date March 24 Revision NumberSheet 2 Modified Txctl Behavior changed signal names Revision Number Revision Date March 24 Sheet 4 # Description Revision Date August 21 Revision Number Revision Date March 24 Sheet 5 DescriptionSheet 1 Initial external release Related Documents What You Will Find in This DocumentDocument General Description Internal Architecture Ball Assignments Ball Cbga Assignments Top ViewSignal Name Ball Balls Listed in Alphabetic Order by Signal NameBall List in Alphanumeric Order by Signal Name Ball List TablesLeddata GND 2CCLKLedclk LedlatchRfclk RxlosintPtpa RMOD0AD6 TxfaultintAB5 AC5UPXDATA7 VDD UPXDATA5 VDDUPXDATA6 VDD UPXDATA8 VDDVDD5 VDD3VDD4 VDD5 AC4 AC8Balls Listed in Alphabetic Order by Ball Location Ball Signal NameBall List in Alphanumeric Order by Ball Location TDAT8 TDAT9RSX TPRTY1 RPRTY1 TPRTY3VDD VDD5 UPXDATA1 VDD GNDGND UPXDATA5 UPXDATA31 UPXDATA11 VDDVDD4 UPXADD8 VDD UPXADD6VDD5 UPXADD7 UPXADD3GND AC3 AC1GND AC2 AC4 VDD5COL2 Datasheet Ball Assignments and Signal Descriptions Naming ConventionsInterface Signal Groups Interface SignalsSignal Name Ball Type Signal Description TablesSPI3 Interface Signal Descriptions Sheet 1 DesignatorSPI3 Interface Signal Descriptions Sheet 2 Signal Name Ball Type Standard DescriptionSPI3 Interface Signal Descriptions Sheet 3 DTPA03 Direct Transmit Packet SPI3 Interface Signal Descriptions Sheet 4Available Polled-PHY Transmit Packet Available SPI3 Interface Signal Descriptions Sheet 5Receive Data Bus SPI3 Interface Signal Descriptions Sheet 6 SPI3 Interface Signal Descriptions Sheet 7 SPI3 Interface Signal Descriptions Sheet 8 SerDes Interface Signal Descriptions Signal Name Ball Designator Type Standard DescriptionTransmit Data Gmii Interface Signal Descriptions Sheet 1Transmit Enable Source Synchronous TransmitCarrier Sense Gmii Interface Signal Descriptions Sheet 2Receive Data Receiver Reference ClockSource Synchronous Transmit Clock Rgmii Interface Signal Descriptions Sheet 1Transmit Control CPU Interface Signal Descriptions Sheet 1 Rgmii Interface Signal Descriptions Sheet 2Receive Control CPU Interface Signal Descriptions Sheet 2 Signal Name Ball Type Standard Description Designator Transmit Pause Control Interface Signal DescriptionsOptical Module Interface Signal Descriptions Sheet 1 Transmit DisableTransmitter Fault Interrupt Optical Module Interface Signal Descriptions Sheet 2Mdio Interface Signal Descriptions Module Definition InterruptSystem Interface Signal Descriptions LED Interface Signal DescriptionsJtag Interface Signal Descriptions SysreslPower Supply Signal Descriptions AC4 AC8Type Quantity Ball Usage SummaryBall Usage Summary Total 552GMII/RGMII/SerDes/OMI Multiplexed Ball Connections Copper Mode Fiber ModeMultiplexed Ball Connections Line Side Interface Multiplexed Balls Sheet 1Line Side Interface Multiplexed Balls Sheet 2 SPI3 Signals Ball Number Comments2 SPI3 MPHY/SPHY Ball Connections SPI3 MPHY/SPHY Interface Sheet 1SPI3 MPHY/SPHY Interface Sheet 2 SPI3 MPHY/SPHY Interface Sheet 3 Ball State During ResetInterface Ball Name Ball Reset State Comment SPI3LED Leddata Jtag TDOCPU GMII/RGMIIPower-Up Sequence Power Supply SequencingPower-Down Sequence Pull-Up/Pull-Down Ball Guidelines Analog Power FilteringPower Supply Power-Up Order Time Delta to Pull-Up/Pull-Down and Unused Ball GuidelinesAnalog Power Supply Filter Network Analog Power Balls Signal Name Ball Comments DesignatorMedia Access Controller MAC Functional DescriptionsAutomatic CRC Generation Features for Fiber and Copper ModePadding of Undersized Frames on Transmit Filtering of Receive PacketsFilter Broadcast Packets Filter CRC Error PacketsFilter on Multicast Packet Match Filter Vlan PacketsCRC Errored Packets Drop Enable Behavior CRC Error DetectionFlow Control 2.1 802.3x Flow Control Full-Duplex Operation Illustrates the Ieee 802.3 Fifo flow control functionsPause Frame Format Packet Buffering FifoPause Settings #%&*#%Half-Duplex Operation Transmit Pause Control InterfaceValid Decodes for TXPAUSEADD20 Operation of TX Pause Control InterfaceKey Configuration Registers ConfigurationMixed-Mode Operation Operational Mode Configuration Registers Fiber ModeRegister Name Description Address Fiber Forced Mode Copper ModeDetermining If Link Is Established in Auto-Negotiation Mode Determination of Link Establishment in Forced ModeDuplex Jumbo Packet SupportSpeed Copper Auto-NegotiationTX Statistics Rx StatisticsLoss-less Flow Control TX and RX Fifo Operation TX Fifo Packet Buffer DimensionsRmon Statistics Support RX FifoRmon Ethernet Statistics Type IXF1104 MAC-Equivalent Rmon Additional Statistics Sheet 1Definition of Rmon Group 1 StatisticsRmon Additional Statistics Sheet 2 ConventionsRmon Ethernet Statistics Type SPI3 Interface AdvantagesData Path Mphy OperationMphy Logical Timing 1.1 SPI3 RX Round Robin Data TransmissionTransmit Timing Receive TimingMode Network ProcessorLine-Side Interface PortParity Sphy ModeClock Rates Receive Data TransmissionTransmit Timing Sphy Sphy Logical TimingReceive Timing Sphy Sphy Receive Logical Timing SPI3 Bus RX SPI3 Flow Control 2.9 SPI3 Flow ControlTX SPI3 Flow Control Stpa Gigabit Media Independent Interface Gmii Pre-Pending FunctionGmii Signal Multiplexing Gmii Interface Signal DefinitionTransmit Reference Clock Gmii Interface Signal DefinitionsGmii Standard Source Description Transmit Data BusReduced Gigabit Media Independent Interface Rgmii Multiplexing of Data and ControlTxer and Rxer Coding Rgmii Signal DefinitionsTiming Specifics Txer and Rxer Coding DescriptionTxctl Behavior 4 10/100 Mbps Functionality Mdio Control and InterfaceIn-Band Status Mdio Register Descriptions Clear When DoneMdio Address MDC GenerationManagement Frames Single MDI Command OperationMDI State Machine MDI State Autoscan Operation FeaturesSerDes Interface Functional DescriptionTransmitter Operational Overview Transmitter Programmable Driver-Power LevelsSerDes Driver TX Power Levels Normalized DRVPWRx3 DRVPWRx2 DRVPWRx1 DRVPWRx0Receiver Operational Overview Selective Power-DownReceiver Jitter Tolerance Transmit Jitter Receive JitterSFP Signal Description Signal Names Optical Module InterfaceHigh-Speed Serial Interface Low-Speed Status Signaling InterfaceFunctional Descriptions MODDEF03Txfaultint TXFAULT03TXDISABLE03 RXLOS033.1 I2C Control and Data Registers 3 I²C Module Configuration Interface3.2 I2C Read Operation 3.3 I2C Write Operation I2C Random Read Transaction3.4 I²C Protocol Specifics Stop Condition Port Protocol Operation Clock and Data TransitionsStart Condition I2CDataDevice Addressing Memory ResetAcknowledge Random Read OperationLED Interface Modes of OperationMode 0 Detailed Operation LED Interface Signal DescriptionPin Name Pin # Pin Description Ledclk Cycle Mode 1 Detailed OperationMode 0 Clock Cycle to Data Bit Relationship Leddata DescriptionLED Data Decodes Power-On, Reset, InitializationMode 1 Clock Cycle to Data Bit Relationship Ledclk Cycle Leddata Name Leddata DescriptionFiber LED Behavior LED Signaling BehaviorLED Behavior Fiber Mode LEDDATA# DecodesCPU Interface LED Behavior Copper ModeCopper LED Behavior Read Access Write AccessEndian CPU Timing ParametersByte Swapper Behavior TAP Interface JtagTAP State Machine Little Endian Big EndianInstruction Register Description Instruction Register and Supported InstructionsInstruction Code Description Data Register Boundary Scan Register Loopback ModesID Register Bypass RegisterLine Side Interface Loopback SPI3 Interface Loopback PathClocks System Interface Reference ClocksMDC Clock 12.2 SPI3 Receive and Transmit ClocksRgmii Clocks 12.1.1 CLK12512.6 I2C Clock Jtag ClockLED Clock Change Port Mode Initialization Sequence Disable Port Sequence Disable and Enable Port SequencesEnable Port Sequence VDD2, VDD3 Parameter Symbol Min Max Units CommentsAbsolute Maximum Ratings TopaParameter Symbol Min Typ Max Units DC SpecificationsRecommended Operating Conditions Parameter Symbol Min Typ Max Units Comments Cmos I/O Cells DC SpecificationsSerDes Transmit Characteristics Sheet 1 Normalized ParameterSerDes Transmit Characteristics Sheet 2 Undershoot / Overshoot SpecificationsRgmii Electrical Characteristics SerDes Receive CharacteristicsRgmii Power Symbol Parameter Conditions Min Max UnitsSPI3 AC Timing Specifications Receive Interface TimingSPI3 Receive Interface Signal Parameters Symbol Parameter Min Max UnitsTransmit Interface Timing SPI3 Transmit Interface TimingSPI3 Transmit Interface Signal Parameters Rgmii Interface Timing Parameters Rgmii AC Timing SpecificationSymbol Parameter Min Typ Max Unit TXC1 1000 Base-T Operation Gmii AC Timing SpecificationGmii 1000BASE-T Transmit Signal Parameters 1.1 1000 BASE-T Transmit InterfaceGmii 1000BASE-T Receive Signal Parameters 1.2 1000BASE-T Receive InterfaceSerDes AC Timing Specification SerDes Timing Diagram SerDes Timing ParametersMDC High-Speed Operation Timing Mdio AC Timing SpecificationMDC Low-Speed Operation Timing Mdio AC Timing Parameter Symbol Min Typ Max Units Test ConditionsMdio Timing Parameters I2C AC Timing Characteristics Sheet 1 Optical Module and I2C AC Timing Specification1 I2C Interface Timing I2C AC Timing Characteristics Sheet 2 CPU Interface Read Cycle AC Timing CPU AC Timing SpecificationCPU Interface Write Cycle AC Timing CPU Interface Write Cycle AC Signal Parameters Symbol Parameter Min MaxTransmit Pause Control AC Timing Specification Transmit Pause Control Interface Timing ParametersJtag AC Timing Specification Jtag AC Timing Jtag AC Timing ParametersSystem AC Timing Specification System Reset AC Timing System Reset AC Timing ParametersLED AC Timing Specification LED Interface AC Timing ParametersDocument Structure Graphical RepresentationRegister Map Register Bit Size Mode OffsetPer Port Registers MAC Control Registers $ Port Index + Offset Sheet 1MAC Control Registers $ Port Index + Offset Sheet 2 MAC RX Statistics Registers $ Port Index + Offset Sheet 1MAC RX Statistics Registers $ Port Index + Offset Sheet 2 MAC TX Statistics Registers $ Port Index + OffsetPHY Autoscan Registers $ Port Index + Offset Global Status and Configuration Registers $ 0x500 0X50CRegister Bit Size Mode Address RX Fifo Registers $ 0x580 0x5BF Sheet 1RX Fifo Registers $ 0x580 0x5BF Sheet 2 TX Fifo Registers $ 0x600 0x63E Sheet 1Mdio Registers $ 0x680 SPI3 Receive Configuration $0x701TX Fifo Registers $ 0x600 0x63E Sheet 2 SPI3 Registers $ 0x700 0x716 Sheet 1SerDes Registers $ 0x780 SPI3 Registers $ 0x700 0x716 Sheet 2Optical Module Registers $ 0x799 0x79F Desired Duplex $ PortIndex + MAC Control RegistersStation Address $ PortIndex +0x00 +0x01 FD FC Type $ PortIndex +Collision Threshold $ PortIndex + FC TX Timer Value $ PortIndex +Collision Distance $ PortIndex + FD FC Address $ PortIndex + 0x08 +IPG Receive Time 2 $ PortIndex + 0x0B IPG Receive Time 1 $ PortIndex + 0x0AIPG Transmit Time $ PortIndex + 0x0C Pause Threshold $ PortIndex + 0x0E Max Frame Size Addr PortIndex + 0x0FMAC if Mode and Rgmii Speed $ PortIndex + Flush TX $ PortIndex +TX Hdfc FC Enable $ PortIndex +FC Back Pressure Length $ PortIndex + TX FdfcShort Runts Threshold $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 1Discard Unknown Control Frame $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 2 TX Config Word $ PortIndex + 0x17 Sheet 1TX Config Word $ PortIndex + 0x17 Sheet 2 Diverse Config Write $ PortIndex + 0x18 Sheet 1Diverse Config Write $ PortIndex + 0x18 Sheet 2 RX Packet Filter Control $ PortIndex + 0x19 Sheet 1RX Packet Filter Control $ PortIndex + 0x19 Sheet 2 Port Multicast Address $ PortIndex +0x1A +0x1BMAC RX Statistics Register Overview MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 1MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 2 Addr PortIndex + 0x0F onMAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 3 Control $ PortIndex + 0x19 is set toMAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 4 MAC TX Statistics Register Overview MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 1MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 2 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 3 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 4 PHY Autoscan RegistersPHY Control $ Port Index + 0x60 Sheet 1 PHY Control $ Port Index + 0x60 Sheet 2 PHY Status $ Port Index + 0x61 Sheet 1PHY Status $ Port Index + 0x61 Sheet 2 PHY Identification 1 $ Port Index +Asmdir PHY Identification 2 $ Port Index +Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 1 100BASE-TXAuto-Negotiation Advertisement $ Port Index + 0x64 Sheet 2 10BASE-TAuto-Negotiation Expansion $ Port Index + 0x66 Sheet 1 Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 2 Auto-Negotiation Next Page Transmit $ Port Index +Port Enable $0x500 Global Status and Configuration Register OverviewInterface Mode $0x501 Link LED Enable $0x502 MAC Soft Reset $0x505CPU Interface $0x508 Mdio Soft Reset $0x506LED Control $0x509 LED Fault Disable $0x50B LED Flash Rate $0x50AJtag ID $0x50C Jedec IDRX Fifo High Watermark Port 1 $0x581 RX Fifo Register OverviewRX Fifo High Watermark Port 0 $0x580 RX Fifo High Watermark Port 2 $0x582RX Fifo Low Watermark Port 1 $0x58B RX Fifo High Watermark Port 3 $0x583RX Fifo Low Watermark Port 0 $0x58A RX FifoRX Fifo Low Watermark Port 3 $0x58D RX Fifo Low Watermark Port 2 $0x58CRX Fifo Overflow Frame Drop Counter Ports 0 3 $0x594 RX Fifo Port Reset $0x59E RX Fifo Errored Frame Drop Enable $0x59F Sheet 1RX Fifo Errored Frame Drop Enable $0x59F Sheet 2 RX Fifo Overflow Event $0x5A0Datasheet 198 RX Fifo SPI3 Loopback Enable for Ports 0 3 $0x5B2 RX Fifo Padding and CRC Strip Enable $0x5B3 RX Fifo Transfer Threshold Port 0 $0x5B8 RX Fifo Transfer Threshold Port 1 $0x5B9RX Fifo Transfer Threshold Port 2 $0x5BA RX Fifo Transfer Threshold Port 3 $0x5BBTX Fifo Register Overview TX Fifo High Watermark Ports 0 3 $0x600Low watermark for TX Fifo Port 1. TX Fifo Low Watermark Register Ports 0 3 $0x60A 0x60DLow watermark for TX Fifo Port 0. Low watermark for TX Fifo Port 2.MAC threshold for TX Fifo Port 1. TX Fifo MAC Threshold Register Ports 0 3 $0x614MAC threshold for TX Fifo Port 0. MAC threshold for TX Fifo Port 2.Register Description TX Fifo Underflow Event Register Description TX Fifo Out of Sequence EventRegister Description TX Fifo Overflow Event FOE2 TX Fifo Port Reset $0x620 Sheet 1Loop RX Data to TX Fifo Line-Side Loopback Ports 0 3 $0x61F FOE1TX Fifo Port Reset $0x620 Sheet 2 TX Fifo Overflow Frame Drop Counter Ports 0 3 $0x621TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625 TX Fifo Port Drop Enable $0x63D TX Fifo Occupancy Counter for Ports 0 3 $0x62DMdio Register Overview Mdio Single Command $0x680Mdio Single Read and Write Data $0x681 Autoscan PHY Address Enable $0x682 Mdio Control $0x683SPHY/MPHY Mode SPI3 Transmit and Global Configuration $0x700 Sheet 19 SPI3 Register Overview Mphy Mode Sphy Mode SPI3 Transmit and Global Configuration $0x700 Sheet 2Sphy Mode Mphy ModeSPI3 Receive Configuration $0x701 Sheet 1 SPI3 Transmit and Global Configuration $0x700 Sheet 3Bit Name Description SPI3 Receive Configuration $0x701 Sheet 2 Sphy Mode Mphy ModeSPI3 Receive Configuration $0x701 Sheet 3 SPI3 Receive Configuration $0x701 Sheet 4 Sphy Mode/MPHY ModeAddress Parity Error Packet Drop Counter $0x70A RX Signal Detect Level Ports 0 3 $0x793 TX Driver Power Level Ports 0 3 $0x784TX and RX Power-Down $0x787 SerDes Register OverviewClock and Interface Mode Change Enable Ports 0 3 $0x794 PortIndex + 0x10 and the Interface Mode $0x501Optical Module Status Ports 0-3 $0x799 Optical Module Register OverviewOptical Module Control Ports 0 3 $0x79A I2C Control Ports 0 3 $0x79B I2C Data Ports 0 3 $0x79FOverview Package SpecificsCbga Package Diagrams Package InformationCbga Package Side View Diagram Flip Chip-Plastic Ball Grid Array Package Diagram FC-PBGA Package Top and Bottom ViewsFC-PBGA Mechanical Specifications Top Label Marking Example Package Marking ExampleHFIXF1104CE.B0 Cbga WFIXF1104CE.B0 Product InformationProduct Number Revision Package RoHS PbgaOrdering Information Sample