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Intel IXF1104 manual Half-Duplex Operation, Transmit Pause Control Interface

Models: IXF1104

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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

5.1.2.1.3Response to Received PAUSE Command Frames

When Flow Control is enabled in the receive direction (bit 0 in the “FC Enable ($ Port_Index + 0x12)"), the IXF1104 responds to PAUSE Command frames received from the link partner as follows:

1.The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex 31B) or has a Destinations Address matching the address programmed in the “Station Address ($ Port_Index +0x00 – +0x01)".

2.If the PAUSE frame is valid, the transmit side of the IXF1104 pauses for the required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.

3.PAUSE does not begin until completion of the frame currently being transmitted.

The IXF1104 response to valid received PAUSE frames is independent of the PAUSE frame filter settings. Refer to Section 5.1.1.3.5, “Filter Pause Packets” on page 68 for additional details.

Note: Pause packets are not filtered if flow control is disabled in bit 0 of the “FC Enable ($ Port_Index + 0x12)”.

5.1.2.1.4Half-Duplex Operation

Transmit flow control is implemented only in half-duplex operation. Upon entering the flow control state, the MAC generates a collision for all subsequent receive packets until exiting the flow control state. Any receive packet in progress when the MAC enters the flow control state will not be collided with but could be lost due if there is insufficient FIFO depth to complete packet reception. Bit 2 of the “FC Enable ($ Port_Index + 0x12)" enables the transmit flow control function.

5.1.2.1.5Transmit Pause Control Interface

The Transmit Pause Control interface allows an external device to trigger the generation of pause frames. The Transmit Pause Control interface is completely asynchronous. It consists of three address signals (TXPAUSEADD[2:0]) and a strobe signal (TXPAUSEFR). The required address for this interface operation is placed on the TXPAUSEADD[2:0] signals and the TXPAUSEFR is pulsed High and returned Low. Refer to Figure 10 “Transmit Pause Control Interface” on page 74 and Table 55 “Transmit Pause Control Interface Timing Parameters” on page 151. Table 23 shows the valid decodes for the TXPAUSEADD[2:0] signals. Figure 10 illustrates the transmit pause control interface.

Note: Flow control must be enabled in the “FC Enable ($ Port_Index + 0x12)” for Transmit Pause Control interface operation.

Note: There are two additional decodes provided that allow the user to generate either an XOFF frame or XON frame from all ports simultaneously.

The default pause quanta for each port is held by the “FC TX Timer Value ($ Port_Index + 0x07)"). The default value of this register is 0x05E after reset is applied.

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Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

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Intel IXF1104 manual Half-Duplex Operation, Transmit Pause Control Interface
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IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.