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Intel IXF1104 manual SerDes Interface Signal Descriptions

Models: IXF1104

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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 4. SerDes Interface Signal Descriptions

Signal Name	Ball Designator	Type	Standard	Description

TX_P_0	Y13
TX_P_1	AD13	Output	SerDes	Transmit Differential Output, Positive.
TX_P_2	W16	Output	SerDes	Transmit Differential Output, Positive.
TX_P_2	W16
TX_P_3	AC18

TX_N_0	Y14
TX_N_1	AD14	Output	SerDes	Transmit Differential Output, Negative.
TX_N_2	Y16	Output	SerDes	Transmit Differential Output, Negative.
TX_N_2	Y16
TX_N_3	AD18

RX_P_0	P22
RX_P_1	V22	Input	SerDes	Receive Differential Input, Positive.1
RX_P_2	T24	Input	SerDes	Receive Differential Input, Positive.1
RX_P_2	T24
RX_P_3	U24

RX_N_0	R22
RX_N_1	U22	Input	SerDes	Receive Differential Input, Negative.1
RX_N_2	R24	Input	SerDes	Receive Differential Input, Negative.1
RX_N_2	R24
RX_N_3	V24

1. Internally terminated differentially with 100 Ω.

Datasheet

Document Number: 278757

Revision Number: 009

Revision Date: 27-Oct-2005

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Intel IXF1104 manual SerDes Interface Signal Descriptions, Signal Name Ball Designator Type Standard Description

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.

Contents

Product Features Datasheet Contents 5.1 105 Applications Figures Tables 134 165 198 Revision Number Revision Date 27-Oct-2005 Revision History182 Revision Number Revision Date August 1, 2005 Sheet 2Globally replaced Gbic with Optical Module Interface Sheet 2 Revision NumberRevision Date March 24 Modified Txctl Behavior changed signal names Revision Number Revision Date March 24 Sheet 4 # Description Sheet 1 Revision Number Revision Date March 24 Sheet 5 DescriptionRevision Date August 21 Initial external release Document What You Will Find in This DocumentRelated Documents General Description Internal Architecture Ball Cbga Assignments Top View Ball AssignmentsBall List Tables Balls Listed in Alphabetic Order by Signal NameBall List in Alphanumeric Order by Signal Name Signal Name BallLedlatch GND 2CCLKLedclk LeddataRMOD0 RxlosintPtpa RfclkAC5 TxfaultintAB5 AD6UPXDATA8 VDD UPXDATA5 VDDUPXDATA6 VDD UPXDATA7 VDDVDD5 AC4 AC8 VDD3VDD4 VDD5Ball List in Alphanumeric Order by Ball Location Ball Signal NameBalls Listed in Alphabetic Order by Ball Location RPRTY1 TPRTY3 TDAT9RSX TPRTY1 TDAT8UPXDATA31 UPXDATA11 VDD VDD GNDGND UPXDATA5 VDD VDD5 UPXDATA1UPXADD3 VDD UPXADD6VDD5 UPXADD7 VDD4 UPXADD8AC4 VDD5 AC1GND AC2 GND AC3COL2 Datasheet Naming Conventions Ball Assignments and Signal DescriptionsInterface Signals Interface Signal GroupsDesignator Signal Description TablesSPI3 Interface Signal Descriptions Sheet 1 Signal Name Ball TypeSignal Name Ball Type Standard Description SPI3 Interface Signal Descriptions Sheet 2SPI3 Interface Signal Descriptions Sheet 3 Available SPI3 Interface Signal Descriptions Sheet 4DTPA03 Direct Transmit Packet Receive Data Bus SPI3 Interface Signal Descriptions Sheet 5Polled-PHY Transmit Packet Available SPI3 Interface Signal Descriptions Sheet 6 SPI3 Interface Signal Descriptions Sheet 7 SPI3 Interface Signal Descriptions Sheet 8 Signal Name Ball Designator Type Standard Description SerDes Interface Signal DescriptionsSource Synchronous Transmit Gmii Interface Signal Descriptions Sheet 1Transmit Enable Transmit DataReceiver Reference Clock Gmii Interface Signal Descriptions Sheet 2Receive Data Carrier SenseTransmit Control Rgmii Interface Signal Descriptions Sheet 1Source Synchronous Transmit Clock Receive Control Rgmii Interface Signal Descriptions Sheet 2CPU Interface Signal Descriptions Sheet 1 CPU Interface Signal Descriptions Sheet 2 Transmit Disable Transmit Pause Control Interface Signal DescriptionsOptical Module Interface Signal Descriptions Sheet 1 Signal Name Ball Type Standard Description DesignatorModule Definition Interrupt Optical Module Interface Signal Descriptions Sheet 2Mdio Interface Signal Descriptions Transmitter Fault InterruptSysresl LED Interface Signal DescriptionsJtag Interface Signal Descriptions System Interface Signal DescriptionsAC4 AC8 Power Supply Signal DescriptionsTotal 552 Ball Usage SummaryBall Usage Summary Type QuantityLine Side Interface Multiplexed Balls Sheet 1 Copper Mode Fiber ModeMultiplexed Ball Connections GMII/RGMII/SerDes/OMI Multiplexed Ball ConnectionsSPI3 MPHY/SPHY Interface Sheet 1 SPI3 Signals Ball Number Comments2 SPI3 MPHY/SPHY Ball Connections Line Side Interface Multiplexed Balls Sheet 2SPI3 MPHY/SPHY Interface Sheet 2 SPI3 Ball State During ResetInterface Ball Name Ball Reset State Comment SPI3 MPHY/SPHY Interface Sheet 3GMII/RGMII Jtag TDOCPU LED LeddataPower-Down Sequence Power Supply SequencingPower-Up Sequence Pull-Up/Pull-Down and Unused Ball Guidelines Analog Power FilteringPower Supply Power-Up Order Time Delta to Pull-Up/Pull-Down Ball GuidelinesSignal Name Ball Comments Designator Analog Power Supply Filter Network Analog Power BallsFunctional Descriptions Media Access Controller MACFiltering of Receive Packets Features for Fiber and Copper ModePadding of Undersized Frames on Transmit Automatic CRC GenerationFilter Vlan Packets Filter CRC Error PacketsFilter on Multicast Packet Match Filter Broadcast PacketsFlow Control CRC Error DetectionCRC Errored Packets Drop Enable Behavior Illustrates the Ieee 802.3 Fifo flow control functions 2.1 802.3x Flow Control Full-Duplex OperationPacket Buffering Fifo Pause Frame Format#%&*#% Pause SettingsTransmit Pause Control Interface Half-Duplex OperationOperation of TX Pause Control Interface Valid Decodes for TXPAUSEADD20Mixed-Mode Operation ConfigurationKey Configuration Registers Register Name Description Address Fiber ModeOperational Mode Configuration Registers Determination of Link Establishment in Forced Mode Copper ModeDetermining If Link Is Established in Auto-Negotiation Mode Fiber Forced ModeCopper Auto-Negotiation Jumbo Packet SupportSpeed DuplexLoss-less Flow Control Rx StatisticsTX Statistics RX Fifo Packet Buffer DimensionsRmon Statistics Support TX and RX Fifo Operation TX FifoGroup 1 Statistics Rmon Additional Statistics Sheet 1Definition of Rmon Rmon Ethernet Statistics Type IXF1104 MAC-EquivalentRmon Ethernet Statistics Type ConventionsRmon Additional Statistics Sheet 2 Advantages SPI3 Interface1.1 SPI3 RX Round Robin Data Transmission Mphy OperationMphy Logical Timing Data PathReceive Timing Transmit TimingPort Network ProcessorLine-Side Interface ModeReceive Data Transmission Sphy ModeClock Rates ParityReceive Timing Sphy Sphy Logical TimingTransmit Timing Sphy Sphy Receive Logical Timing SPI3 Bus TX SPI3 Flow Control 2.9 SPI3 Flow ControlRX SPI3 Flow Control Stpa Pre-Pending Function Gigabit Media Independent Interface GmiiGmii Interface Signal Definition Gmii Signal MultiplexingTransmit Data Bus Gmii Interface Signal DefinitionsGmii Standard Source Description Transmit Reference ClockMultiplexing of Data and Control Reduced Gigabit Media Independent Interface RgmiiTxer and Rxer Coding Description Rgmii Signal DefinitionsTiming Specifics Txer and Rxer CodingTxctl Behavior In-Band Status Mdio Control and Interface4 10/100 Mbps Functionality MDC Generation Clear When DoneMdio Address Mdio Register DescriptionsMDI State Machine Single MDI Command OperationManagement Frames MDI State Functional Description FeaturesSerDes Interface Autoscan OperationNormalized DRVPWRx3 DRVPWRx2 DRVPWRx1 DRVPWRx0 Transmitter Programmable Driver-Power LevelsSerDes Driver TX Power Levels Transmitter Operational OverviewReceiver Jitter Tolerance Selective Power-DownReceiver Operational Overview Receive Jitter Transmit JitterOptical Module Interface SFP Signal Description Signal NamesMODDEF03 Low-Speed Status Signaling InterfaceFunctional Descriptions High-Speed Serial InterfaceRXLOS03 TXFAULT03TXDISABLE03 Txfaultint3.2 I2C Read Operation 3 I²C Module Configuration Interface3.1 I2C Control and Data Registers I2C Random Read Transaction 3.3 I2C Write Operation3.4 I²C Protocol Specifics I2CData Port Protocol Operation Clock and Data TransitionsStart Condition Stop ConditionRandom Read Operation Memory ResetAcknowledge Device AddressingModes of Operation LED InterfacePin Name Pin # Pin Description LED Interface Signal DescriptionMode 0 Detailed Operation Leddata Description Mode 1 Detailed OperationMode 0 Clock Cycle to Data Bit Relationship Ledclk CycleLedclk Cycle Leddata Name Leddata Description Power-On, Reset, InitializationMode 1 Clock Cycle to Data Bit Relationship LED Data DecodesLEDDATA# Decodes LED Signaling BehaviorLED Behavior Fiber Mode Fiber LED BehaviorCopper LED Behavior LED Behavior Copper ModeCPU Interface Write Access Read AccessCPU Timing Parameters EndianLittle Endian Big Endian TAP Interface JtagTAP State Machine Byte Swapper BehaviorInstruction Code Description Data Register Instruction Register and Supported InstructionsInstruction Register Description Bypass Register Loopback ModesID Register Boundary Scan RegisterSPI3 Interface Loopback Path Line Side Interface LoopbackSystem Interface Reference Clocks Clocks12.1.1 CLK125 12.2 SPI3 Receive and Transmit ClocksRgmii Clocks MDC ClockLED Clock Jtag Clock12.6 I2C Clock Change Port Mode Initialization Sequence Enable Port Sequence Disable and Enable Port SequencesDisable Port Sequence Topa Parameter Symbol Min Max Units CommentsAbsolute Maximum Ratings VDD2, VDD3Recommended Operating Conditions DC SpecificationsParameter Symbol Min Typ Max Units Normalized Parameter DC SpecificationsSerDes Transmit Characteristics Sheet 1 Parameter Symbol Min Typ Max Units Comments Cmos I/O CellsSerDes Receive Characteristics Undershoot / Overshoot SpecificationsRgmii Electrical Characteristics SerDes Transmit Characteristics Sheet 2Symbol Parameter Conditions Min Max Units Rgmii PowerReceive Interface Timing SPI3 AC Timing SpecificationsSymbol Parameter Min Max Units SPI3 Receive Interface Signal ParametersSPI3 Transmit Interface Timing Transmit Interface TimingSPI3 Transmit Interface Signal Parameters TXC Rgmii AC Timing SpecificationSymbol Parameter Min Typ Max Unit Rgmii Interface Timing Parameters1.1 1000 BASE-T Transmit Interface Gmii AC Timing SpecificationGmii 1000BASE-T Transmit Signal Parameters 1 1000 Base-T Operation1.2 1000BASE-T Receive Interface Gmii 1000BASE-T Receive Signal ParametersSerDes Timing Diagram SerDes Timing Parameters SerDes AC Timing SpecificationMDC Low-Speed Operation Timing Mdio AC Timing SpecificationMDC High-Speed Operation Timing Mdio Timing Parameters Parameter Symbol Min Typ Max Units Test ConditionsMdio AC Timing 1 I2C Interface Timing Optical Module and I2C AC Timing SpecificationI2C AC Timing Characteristics Sheet 1 I2C AC Timing Characteristics Sheet 2 CPU Interface Write Cycle AC Timing CPU AC Timing SpecificationCPU Interface Read Cycle AC Timing Symbol Parameter Min Max CPU Interface Write Cycle AC Signal ParametersTransmit Pause Control Interface Timing Parameters Transmit Pause Control AC Timing SpecificationJtag AC Timing Jtag AC Timing Parameters Jtag AC Timing SpecificationSystem Reset AC Timing System Reset AC Timing Parameters System AC Timing SpecificationLED Interface AC Timing Parameters LED AC Timing SpecificationGraphical Representation Document StructureMAC Control Registers $ Port Index + Offset Sheet 1 Register Bit Size Mode OffsetPer Port Registers Register MapMAC RX Statistics Registers $ Port Index + Offset Sheet 1 MAC Control Registers $ Port Index + Offset Sheet 2MAC TX Statistics Registers $ Port Index + Offset MAC RX Statistics Registers $ Port Index + Offset Sheet 2RX Fifo Registers $ 0x580 0x5BF Sheet 1 Global Status and Configuration Registers $ 0x500 0X50CRegister Bit Size Mode Address PHY Autoscan Registers $ Port Index + OffsetTX Fifo Registers $ 0x600 0x63E Sheet 1 RX Fifo Registers $ 0x580 0x5BF Sheet 2SPI3 Registers $ 0x700 0x716 Sheet 1 SPI3 Receive Configuration $0x701TX Fifo Registers $ 0x600 0x63E Sheet 2 Mdio Registers $ 0x680Optical Module Registers $ 0x799 0x79F SPI3 Registers $ 0x700 0x716 Sheet 2SerDes Registers $ 0x780 FD FC Type $ PortIndex + MAC Control RegistersStation Address $ PortIndex +0x00 +0x01 Desired Duplex $ PortIndex +FD FC Address $ PortIndex + 0x08 + FC TX Timer Value $ PortIndex +Collision Distance $ PortIndex + Collision Threshold $ PortIndex +IPG Transmit Time $ PortIndex + 0x0C IPG Receive Time 1 $ PortIndex + 0x0AIPG Receive Time 2 $ PortIndex + 0x0B Max Frame Size Addr PortIndex + 0x0F Pause Threshold $ PortIndex + 0x0EFlush TX $ PortIndex + MAC if Mode and Rgmii Speed $ PortIndex +TX Fdfc FC Enable $ PortIndex +FC Back Pressure Length $ PortIndex + TX HdfcDiscard Unknown Control Frame $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 1Short Runts Threshold $ PortIndex + TX Config Word $ PortIndex + 0x17 Sheet 1 RX Config Word $ PortIndex + 0x16 Sheet 2Diverse Config Write $ PortIndex + 0x18 Sheet 1 TX Config Word $ PortIndex + 0x17 Sheet 2RX Packet Filter Control $ PortIndex + 0x19 Sheet 1 Diverse Config Write $ PortIndex + 0x18 Sheet 2Port Multicast Address $ PortIndex +0x1A +0x1B RX Packet Filter Control $ PortIndex + 0x19 Sheet 2MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 1 MAC RX Statistics Register OverviewAddr PortIndex + 0x0F on MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 2Control $ PortIndex + 0x19 is set to MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 3MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 4 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 1 MAC TX Statistics Register OverviewMAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 2 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 3 PHY Control $ Port Index + 0x60 Sheet 1 PHY Autoscan RegistersMAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 4 PHY Status $ Port Index + 0x61 Sheet 1 PHY Control $ Port Index + 0x60 Sheet 2PHY Identification 1 $ Port Index + PHY Status $ Port Index + 0x61 Sheet 2100BASE-TX PHY Identification 2 $ Port Index +Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 1 Asmdir10BASE-T Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 2Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 1 Auto-Negotiation Next Page Transmit $ Port Index + Auto-Negotiation Expansion $ Port Index + 0x66 Sheet 2Interface Mode $0x501 Global Status and Configuration Register OverviewPort Enable $0x500 MAC Soft Reset $0x505 Link LED Enable $0x502LED Control $0x509 Mdio Soft Reset $0x506CPU Interface $0x508 LED Flash Rate $0x50A LED Fault Disable $0x50BJedec ID Jtag ID $0x50CRX Fifo High Watermark Port 2 $0x582 RX Fifo Register OverviewRX Fifo High Watermark Port 0 $0x580 RX Fifo High Watermark Port 1 $0x581RX Fifo RX Fifo High Watermark Port 3 $0x583RX Fifo Low Watermark Port 0 $0x58A RX Fifo Low Watermark Port 1 $0x58BRX Fifo Overflow Frame Drop Counter Ports 0 3 $0x594 RX Fifo Low Watermark Port 2 $0x58CRX Fifo Low Watermark Port 3 $0x58D RX Fifo Errored Frame Drop Enable $0x59F Sheet 1 RX Fifo Port Reset $0x59ERX Fifo Overflow Event $0x5A0 RX Fifo Errored Frame Drop Enable $0x59F Sheet 2Datasheet 198 RX Fifo SPI3 Loopback Enable for Ports 0 3 $0x5B2 RX Fifo Padding and CRC Strip Enable $0x5B3 RX Fifo Transfer Threshold Port 1 $0x5B9 RX Fifo Transfer Threshold Port 0 $0x5B8RX Fifo Transfer Threshold Port 3 $0x5BB RX Fifo Transfer Threshold Port 2 $0x5BATX Fifo High Watermark Ports 0 3 $0x600 TX Fifo Register OverviewLow watermark for TX Fifo Port 2. TX Fifo Low Watermark Register Ports 0 3 $0x60A 0x60DLow watermark for TX Fifo Port 0. Low watermark for TX Fifo Port 1.MAC threshold for TX Fifo Port 2. TX Fifo MAC Threshold Register Ports 0 3 $0x614MAC threshold for TX Fifo Port 0. MAC threshold for TX Fifo Port 1.Register Description TX Fifo Overflow Event Register Description TX Fifo Out of Sequence EventRegister Description TX Fifo Underflow Event FOE1 TX Fifo Port Reset $0x620 Sheet 1Loop RX Data to TX Fifo Line-Side Loopback Ports 0 3 $0x61F FOE2TX Fifo Overflow Frame Drop Counter Ports 0 3 $0x621 TX Fifo Port Reset $0x620 Sheet 2TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625 TX Fifo Occupancy Counter for Ports 0 3 $0x62D TX Fifo Port Drop Enable $0x63DMdio Single Read and Write Data $0x681 Mdio Single Command $0x680Mdio Register Overview Mdio Control $0x683 Autoscan PHY Address Enable $0x6829 SPI3 Register Overview SPI3 Transmit and Global Configuration $0x700 Sheet 1SPHY/MPHY Mode Mphy Mode SPI3 Transmit and Global Configuration $0x700 Sheet 2Sphy Mode Mphy Mode Sphy ModeBit Name Description SPI3 Transmit and Global Configuration $0x700 Sheet 3SPI3 Receive Configuration $0x701 Sheet 1 Sphy Mode Mphy Mode SPI3 Receive Configuration $0x701 Sheet 2SPI3 Receive Configuration $0x701 Sheet 3 Sphy Mode/MPHY Mode SPI3 Receive Configuration $0x701 Sheet 4Address Parity Error Packet Drop Counter $0x70A SerDes Register Overview TX Driver Power Level Ports 0 3 $0x784TX and RX Power-Down $0x787 RX Signal Detect Level Ports 0 3 $0x793PortIndex + 0x10 and the Interface Mode $0x501 Clock and Interface Mode Change Enable Ports 0 3 $0x794Optical Module Control Ports 0 3 $0x79A Optical Module Register OverviewOptical Module Status Ports 0-3 $0x799 I2C Data Ports 0 3 $0x79F I2C Control Ports 0 3 $0x79BPackage Specifics OverviewPackage Information Cbga Package DiagramsCbga Package Side View Diagram FC-PBGA Package Top and Bottom Views Flip Chip-Plastic Ball Grid Array Package DiagramFC-PBGA Mechanical Specifications Package Marking Example Top Label Marking ExamplePbga Product InformationProduct Number Revision Package RoHS HFIXF1104CE.B0 Cbga WFIXF1104CE.B0Ordering Information Sample